Increased terrace configuration for non-volatile memory

• US 10,726,921 B2
• Filed: 03/30/2018
• Issued: 07/28/2020
• Est. Priority Date: 09/19/2017
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Hsiung, Chia-Lin, Toyama, Fumiaki, Tseng, Tai-Yuan, Li, Yan
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US15/942,044
• Publication Number:
  US 20190088335A1
• Time in Patent Office: 851 Days
• Field of Search: 36518511, 36523006, 36523003
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A three-dimensional block includes a stack comprising a plurality of control gate layers configured to bias memory cells of the block. The block includes a plurality of track regions that includes three or more hookup regions. The plurality of track regions separate the memory cells into three memory cell regions. Tracks extending in the track regions supply voltages to the hookup regions. A system includes a memory plane of blocks, and a plurality of track regions, each extending across the memory plane of blocks.

Claims

1. An apparatus comprising:

a stack comprising a plurality of control gate layers;

a first set of memory cells configured to be biased by the stack of control gate layers;

a second set of memory cells configured to be biased by the stack of control gate layers;

a first track region separating the first set of memory cells from the second set of memory cells;

a first set of tracks extending in the first track region and configured to bias a first set of control gate layers of the stack of control gate layers; and

a second set of tracks extending in a second track region separate from the first track region and configured to bias a second set of control gate layers of the stack of the control gate layers.

2. The apparatus of claim 1, further comprising a third set of memory cells configured to be biased by the stack of control gate layers, wherein the second track region separates the second set of memory cells from the third set of memory cells.

3. The apparatus of claim 2, wherein the second set of tracks extends through the second track region.

4. The apparatus of claim 1, further comprising:

a row decoder comprising;

a first portion configured to supply a first set of voltages to the first set of tracks; and

a second portion configured to supply a second set of voltages to the second set of tracks.

5. The apparatus of claim 4, wherein the first portion and the second portion are in-array components of a same memory cell region in which the second set of memory cells are disposed.

6. The apparatus of claim 5, wherein the first portion and the second portion are in-array components of different memory cell regions.

7. The apparatus of claim 1, wherein the first set of control gate layers comprises an upper set of control gate layers of the stack and the second set of control gate layers comprises a lower set of control gate layers of the stack.

9. The apparatus of claim 1, wherein the row decoder comprises:

a first portion configured to output the first set of voltages; and

a second portion configured to output the second set of voltages.

10. The apparatus of claim 9, wherein the first portion and the second portion are in-array components of a same memory cell region.

11. The apparatus of claim 9, wherein the first portion and the second portion are in-array components of different memory cell regions.

12. The apparatus of claim 9, wherein the stack comprises a first stack, wherein the apparatus further comprises a second stack of control gate layers, and wherein the row decoder further comprises:

a third portion configured to output a third set of voltages to a first set of control gate layers of the second stack by way of a third set of tracks extending through the first track region.

13. The apparatus of claim 12, wherein the row decoder further comprises:

a fourth portion configured to output a fourth set of voltages to a second set of control gate layers of the second stack.

14. The apparatus of claim 13, wherein the third portion and the fourth portion are in-array components of different memory cell regions.

15. The apparatus of claim 14, wherein the third portion and the fourth portion are each in-array components of memory cell regions different from the memory cell regions of which the first and second portions are in-array components.

8. An apparatus comprising:

a stack comprising a plurality of control gate layers configured to bias a plurality of memory cells; and

a row decoder configured to;

output a first set of voltages to a first set of the control gate layers of the stack by way of a first set of tracks extending through a first track region; and

output a second set of voltages to a second set of control gate layers of the stack by way of a second set of tracks extending through a second track region separate from the first track region.

16. The apparatus of claim 8, wherein the first set of control gate layers comprises an upper set of control gate layers of the stack and the second set of control gate layers comprises a lower set of control gate layers of the stack.

17. A method comprising:

outputting, with a first row decoder portion, a first control gate voltage associated with a first memory operation;

supplying, with a first track coupled to the first row decoder portion, the first control gate voltage through a first track region to a first control gate layer of a stack;

outputting, with a second row decoder portion, a second control gate voltage associated with a second memory operation; and

supplying, with a second track coupled to the second row decoder, the second control gate voltage through a second track region to a second control gate layer of the stack,

wherein the first track region is separate from the second track region.