Method for manufacturing semiconductor structure with mask structure

• US 10,727,068 B2
• Filed: 10/08/2019
• Issued: 07/28/2020
• Est. Priority Date: 11/06/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Hsin-Ying, Wang, Mei-Yun, Wang, Hsien-Cheng, Yang, Fu-Kai, Liu, Shih-Wen, Hsu, Hsiao-Chiu
• Primary Examiner(s): Wall, Vincent
• Application Number:
  US16/596,518
• Publication Number:
  US 20200051821A1
• Time in Patent Office: 294 Days
• Field of Search: None
• CPC Class Codes: H01L 21/0334 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

Semiconductor structures and methods for forming the same are provided. The method includes forming a dummy gate structure and forming a spacer on a lower portion of a sidewall of the dummy gate structure and exposing an upper portion of the sidewall of the dummy gate structure. The method further includes forming a dielectric layer covering the upper portion of the sidewall of the dummy gate structure exposed by the spacer and removing the dummy gate structure to form a tube-shaped trench. The method further includes removing a portion of the dielectric layer to form a cone-shaped trench and forming a gate structure in a bottom portion of the tube-shaped trench. The method further includes forming a hard mask structure in the cone-shaped trench and an upper portion of the tube-shaped trench, and an interface between the hard mask structure and the dielectric layer overlaps the spacer.

Claims

1. A method for forming a semiconductor structure, comprising:

forming a dummy gate structure over a substrate;

forming a spacer on a lower portion of a sidewall of the dummy gate structure and exposing an upper portion of the sidewall of the dummy gate structure;

forming a source/drain region in the substrate;

forming a dielectric layer covering the upper portion of the sidewall of the dummy gate structure exposed by the spacer;

removing the dummy gate structure to form a tube-shaped trench;

removing a portion of the dielectric layer to form a cone-shaped trench over the tube-shaped trench;

forming a gate structure in a bottom portion of the tube-shaped trench;

forming a hard mask structure in the cone-shaped trench and an upper portion of the tube-shaped trench;

forming a contact over the source/drain structure, wherein the contact has an extending portion covering a top surface of the hard mask structure; and

polishing the contact to remove the extending portion of the contact,

wherein an interface between the hard mask structure and the dielectric layer overlaps the spacer and the source/drain region.

2. The method for forming a semiconductor structure as claimed in claim 1, wherein the extending portion of the contact overlaps the dielectric layer.

3. The method for forming a semiconductor structure as claimed in claim 1, wherein the extending portion of the contact has a lateral width in a range from about 3 nm to about 100 nm.

4. The method for forming a semiconductor structure as claimed in claim 1, wherein the hard mask structure has a slope sidewall overlapping an outmost sidewall of the spacer.

5. The method for forming a semiconductor structure as claimed in claim 1, wherein an interface between the gate structure and the hard mask structure is lower than a topmost point of the spacer.

6. The method for forming a semiconductor structure as claimed in claim 1, wherein an interface between the gate structure and the hard mask structure is lower than a top surface of the contact.

7. The method for forming a semiconductor structure as claimed in claim 1, wherein a first width of a top surface of the hard mask structure is greater than a second width of a bottom surface of the hard mask structure, and the second width of the bottom surface of the hard mask structure is substantially equal to a width of the gate structure.

8. A method for forming a semiconductor structure, comprising:

forming a dummy gate structure over a substrate;

forming a spacer on a sidewall of the dummy gate structure;

forming a resist layer covering a lower portion of the spacer and exposing an upper portion of the spacer;

removing the upper portion of the spacer exposed by the resist layer, thereby only a lower sidewall of the dummy gate structure is covered by the spacer;

removing the resist layer;

forming a dielectric layer on an upper sidewall of the dummy gate structure;

removing the dummy gate structure to form a trench;

removing a portion of the dielectric layer to form a slope sidewall;

forming a gate structure in a bottom portion of the trench; and

forming a hard mask structure over the gate structure, wherein the hard mask structure covers the slope sidewall of the dielectric layer.

9. The method for forming a semiconductor structure as claimed in claim 8, wherein the spacer completely overlaps with the hard mask structure.

10. The method for forming a semiconductor structure as claimed in claim 8, wherein the hard mask structure is in direct contact with the slope sidewall of the dielectric layer.

11. The method for forming a semiconductor structure as claimed in claim 8, wherein an angle between the slope sidewall of the dielectric layer and a sidewall of the trench is in a range from about 120 to about 165.

12. The method for forming a semiconductor structure as claimed in claim 8, further comprising:

forming an interlayer dielectric layer over the dielectric layer before removing the dummy gate structure to form the trench; and

removing a portion of the interlayer dielectric layer to form a cone-shape trench surrounded by the interlayer dielectric layer and the dielectric layer.

13. The method for forming a semiconductor structure as claimed in claim 12, further comprising:

forming a contact through the interlayer dielectric layer, wherein an extending portion of the contact overlaps the hard mask structure, the interlayer dielectric layer, and the dielectric layer.

14. The method for forming a semiconductor structure as claimed in claim 13, further comprising:

removing the extending portion of the contact.

15. A method for forming a semiconductor structure, comprising:

forming a dummy gate structure over a substrate;

forming a sealing layer on a lower portion of a sidewall of the dummy gate structure;

forming a dielectric layer on an upper portion of the sidewall of the dummy gate structure;

removing the dummy gate structure to form a trench having a substantially straight sidewall formed of a sidewall of the sealing layer and a sidewall of the dielectric layer;

etching the dielectric layer to form a slope sidewall, thereby forming a funnel shaped trench by the slope sidewall of the dielectric layer and the sidewall of the sealing layer;

forming a gate structure in the funnel shaped trench; and

forming a hard mask structure in the funnel shaped trench, wherein the hard mask structure is in direct contact with the sidewall of the sealing layer and the slope sidewall of the dielectric layer.

16. The method for forming a semiconductor structure as claimed in claim 15, further comprising:

forming a spacer over the sealing layer, wherein a top of the spacer is substantially level with a top of the sealing layer.

17. The method for forming a semiconductor structure as claimed in claim 16, wherein the hard mask structure overlaps an outmost sidewall of the spacer.

18. The method for forming a semiconductor structure as claimed in claim 17, further comprising:

forming a source/drain structure in the substrate, wherein the hard mask structure overlaps the source/drain structure.

19. The method for forming a semiconductor structure as claimed in claim 15, wherein the hard mask structure has a cone-shaped top portion and a tube-shaped bottom portion.

20. The method for forming a semiconductor structure as claimed in claim 19, wherein a lateral distance between an outer edge of the tube shaped bottom portion of the hard mask structure and an outer edge of the cone-shaped top portion of the hard mask structure is in a range from about 3 nm to about 100 nm.