Structure and formation method of fin-like field effect transistor

• US 10,727,137 B2
• Filed: 07/02/2018
• Issued: 07/28/2020
• Est. Priority Date: 06/12/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Jangjian, Shiu-Ko, Lin, Tzu Kai, Jeng, Chi-Cherng
• Primary Examiner(s): Pham, Long
• Application Number:
  US16/025,786
• Publication Number:
  US 20180323112A1
• Time in Patent Office: 757 Days
• Field of Search: None
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure.

Claims

1. A semiconductor device structure, comprising:

a fin structure extending over a semiconductor substrate;

a gate stack covering a portion of the fin structure;

an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack;

a semiconductor protection layer over the epitaxially grown source/drain structure, wherein the semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure;

a dielectric layer over the semiconductor substrate; and

a contact hole extending through the dielectric layer to a first portion of the semiconductor protection layer, wherein the semiconductor protection layer has a first thickness at the first portion and a second thickness under the dielectric layer, wherein the second thickness is greater than the first thickness.

2. The semiconductor device structure of claim 1, wherein the semiconductor protection layer is not between the gate stack and the portion of the fin structure covered by the gate stack.

3. The semiconductor device structure of claim 1, wherein the semiconductor protection layer is in direct contact with the epitaxially grown source/drain structure.

4. The semiconductor device structure of claim 1, wherein the semiconductor protection layer is made of a substantially pure silicon material.

5. The semiconductor device structure of claim 1, wherein the atomic concentration of silicon of the semiconductor protection layer is in a range from about 50% to about 99%.

6. The semiconductor device structure of claim 1, wherein the atomic concentration of silicon of the semiconductor protection layer gradually decreases along a direction from a surface of the semiconductor protection layer towards the epitaxially grown source/drain structure.

7. The semiconductor device structure of claim 1, wherein the first thickness is between approximately 2 nm and about 10 nm.

8. The semiconductor device structure of claim 1, wherein the semiconductor protection layer is disposed on a first portion of a surface of the epitaxially grown source/drain structure and a support element is disposed on a second portion of the surface of the epitaxially grown source/drain structure.

9. The semiconductor device structure of claim 8, wherein the support element is at least one of silicon nitride, silicon oxynitride, or silicon carbide.

10. The semiconductor device structure of claim 8, wherein the support element interfaces the semiconductor protection layer.

11. A semiconductor device structure, comprising:

a first fin structure extending from a semiconductor substrate;

a gate stack covering a portion of the first fin structure;

a first epitaxially grown source/drain structure over the first fin structure;

a second fin structure over the semiconductor substrate;

a second epitaxially grown source/drain structure over the second fin structure;

a first semiconductor protection layer over the first epitaxially grown source/drain structure, wherein the first semiconductor protection layer has an atomic concentration of silicon greater than that of the first epitaxially grown source/drain structure, wherein the first semiconductor protection layer has a first terminal edge adjacent a support element and a second terminal edge adjacent a spacer element disposed on a sidewall of the gate stack, wherein the first semiconductor protection layer has a first thickness at a first region and a second thickness at a second region, the first thickness less than the second thickness; and

a second semiconductor protection layer over the second epitaxially grown source/drain structure, wherein the second semiconductor protection layer has an atomic concentration of silicon greater than that of the second epitaxially grown source/drain structure.

12. The semiconductor device structure of claim 11, wherein the second semiconductor protection layer has a first terminal edge abutting an isolation feature extending between the first and second fin structures and a second terminal edge abutting spacer elements of a second gate stack over the second fin structure.

13. The semiconductor device structure of claim 11, wherein the second semiconductor protection layer has the second thickness.

14. The semiconductor device structure of claim 11, wherein the first region is within a contact hole.

15. The semiconductor device structure of claim 11, wherein at least one of the first semiconductor protection layer and the second semiconductor protection layer is made of a substantially pure silicon material.

16. The semiconductor device structure of claim 11, wherein the atomic concentration of silicon of the first semiconductor protection layer or the second semiconductor protection layer is in a range from about 50% to about 99%.

17. The semiconductor device structure of claim 16, wherein the atomic concentration of silicon of the first semiconductor protection layer gradually decreases along a direction from a surface of the first semiconductor protection layer towards the first epitaxially grown source/drain structure.

18. A semiconductor device structure, comprising:

a first fin structure and a second fin structure over a semiconductor substrate;

a first gate stack over a portion of the first fin structure and a second gate stack over a portion of the second fin structure;

a first source/drain structure adjacent the first gate stack and a second source/drain structure adjacent the second gate stack;

a protection layer having a first portion over the first source/drain structure and a second portion over the second source/drain structure, wherein the protection layer has an atomic concentration of silicon greater than that of the first source/drain structure and the second source/drain structure; and

a dielectric layer over the protection layer, the first source/drain structure and the second source/drain structure, wherein an opening in the dielectric layer exposes the first portion of the protection layer having a first thickness, the first thickness being less than a second thickness of the second portion of the protection layer.

19. The semiconductor device of claim 18, wherein the opening in the dielectric layer provides a contact hole.

20. The semiconductor device of claim 18, wherein the first portion of the protection layer interfaces support elements disposed on sidewalls of the first source/drain structure.