Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same

• US 10,727,252 B2
• Filed: 01/16/2018
• Issued: 07/28/2020
• Est. Priority Date: 03/13/2008
• Status: Expired due to Fees

• Current Assignee: RPX Corporation
• Original Assignee: Tela Innovations, Inc.
• Inventors: Becker, Scott T., Mali, Jim, Lambert, Carole
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US15/872,893
• Publication Number:
  US 20180175061A1
• Time in Patent Office: 924 Days
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 2027/11853 Sub-micron technology
• CPC Class Codes: H01L 2027/11875 Wiring region, routing
• CPC Class Codes: H01L 2027/11887 Three levels of metal
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/49844 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/5386 Geometry or layout of the interconnection structure
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/10 SRAM devices comprising bipolar components
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration.

Claims

1. A semiconductor chip, comprising:

a first conductive structure forming a gate electrode of a first transistor of a first transistor type;

a second conductive structure forming a gate electrode of a second transistor of the first transistor type,

wherein both the first transistor of the first transistor type and the second transistor of the first transistor type are part of a cross-coupled transistor configuration, and

wherein a diffusion region of the first transistor of the first transistor type is physically separated from a diffusion region of the second transistor of the first transistor type; and

a first interconnect conductive structure, wherein the diffusion region of the first transistor of the first transistor type is electrically connected to the diffusion region of the second transistor of the first transistor type through a linear-shaped portion of the first interconnect conductive structure.

2. The semiconductor chip as recited in claim 1, wherein the first conductive structure is linear-shaped, and wherein the second conductive structure is linear-shaped.

3. The semiconductor chip as recited in claim 2, wherein each of the first conductive structure and the second conductive structure extend lengthwise in a first direction.

4. The semiconductor chip as recited in claim 3, wherein the linear-shaped portion of the first interconnect conductive structure extends lengthwise in a second direction perpendicular to the first direction.

5. The semiconductor chip as recited in claim 3, wherein the first conductive structure and the second conductive structure have a substantially equal length as measured in the first direction.

6. The semiconductor chip as recited in claim 5, wherein a first end of the first conductive structure is substantially aligned with a first end of the second conductive structure in the first direction, and wherein a second end of the first conductive structure is substantially aligned with a second end of the second conductive structure in the first direction.

7. The semiconductor chip as recited in claim 3, further comprising:

a first gate contact formed to contact the first conductive structure; and

a second gate contact formed to contact the second conductive structure, wherein the first gate contact is substantially aligned with the second gate contact in the first direction.

8. The semiconductor chip as recited in claim 7, further comprising:

a first diffusion contact formed to contact the diffusion region of the first transistor of the first transistor type; and

a second diffusion contact formed to contact the diffusion region of the second transistor of the first transistor type, wherein the first diffusion contact is substantially aligned with the second diffusion contact in the first direction.

9. The semiconductor chip as recited in claim 3, further comprising:

a third conductive structure forming a gate electrode of a first transistor of a second transistor type; and

a fourth conductive structure forming a gate electrode of a second transistor of the second transistor type, wherein both the first transistor of the second transistor type and the second transistor of the second transistor type are part of the cross-coupled transistor configuration.

10. The semiconductor chip as recited in claim 9, wherein the third conductive structure is linear-shaped, and wherein the fourth conductive structure is linear-shaped.

11. The semiconductor chip as recited in claim 10, wherein each of the third conductive structure and the fourth conductive structure extend lengthwise in the first direction.

12. The semiconductor chip as recited in claim 10, wherein the first transistor of the second transistor type and the second transistor of the second transistor type are formed in part by a shared diffusion region.

13. The semiconductor chip as recited in claim 12, wherein the shared diffusion region is electrically connected to both the diffusion region of the first transistor of the first transistor type and the diffusion region of the second transistor of the first transistor type.

14. The semiconductor chip as recited in claim 13, wherein a lengthwise centerline of the third conductive structure is substantially aligned with a lengthwise centerline of the first conductive structure.

15. The semiconductor chip as recited in claim 14, wherein a distance measured in a second direction perpendicular to the first direction between the lengthwise centerline of the first conductive structure and a lengthwise centerline of the second conductive structure is substantially equal to two times a distance measured in the second direction between the lengthwise centerline of the third conductive structure and a lengthwise centerline of the fourth conductive structure.

16. The semiconductor chip as recited in claim 13, wherein the first conductive structure is electrically connected to the fourth conductive structure, and wherein the second conductive structure is electrically connected to the third conductive structure.

17. The semiconductor chip as recited in claim 16, further comprising:

a second interconnect conductive structure, wherein the first conductive structure is electrically connected to the fourth conductive structure through the second interconnect conductive structure; and

a third interconnect conductive structure, wherein the second conductive structure is electrically connected to the third conductive structure through the third interconnect conductive structure.

18. The semiconductor chip as recited in claim 17, wherein the first interconnect conductive structure, the second interconnect conductive structure, and the third interconnect conductive structure are formed in a same interconnect level of the semiconductor chip.

19. The semiconductor chip as recited in claim 18, wherein a lengthwise centerline of the third conductive structure is substantially aligned with a lengthwise centerline of the first conductive structure, and wherein a lengthwise centerline of the fourth conductive structure is not aligned with a lengthwise centerline of the second conductive structure.

20. The semiconductor chip as recited in claim 19, wherein the third conductive structure and the fourth conductive structure have a substantially equal length as measured in the first direction.