Nanosheet transistor

• US 10,727,315 B2
• Filed: 01/20/2019
• Issued: 07/28/2020
• Est. Priority Date: 11/15/2017
• Status: Active Grant

• Current Assignee: Tessera (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Cheng, Kangguo, Li, Juntao, Wu, Heng, Xu, Peng
• Primary Examiner(s): Patel, Reema
• Application Number:
  US16/252,663
• Publication Number:
  US 20190157420A1
• Time in Patent Office: 555 Days
• Field of Search: None
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

Claims

1. A nanosheet field-effect transistor device, comprising:

a vertical stack of nanosheet channel layers;

a plurality of all-around gate stacks operatively associated with the nanosheet channel layers, the all-around gate stacks including a gate dielectric layer and metal gate material;

a gate electrode extending vertically from a top surface of the plurality of all-around gate stacks and including first and second vertical sidewalls;

first and second epitaxial source/drain regions operatively associated with the nanosheet channel layers;

a dielectric liner including;

first and second liner portions extending, respectively, over the first and second epitaxial source/drain regions, and

first and second outer spacer portions extending, respectively, over the first and second vertical sidewalls of the gate electrode,

wherein the first and second liner portions of the dielectric liner are integral, respectively, with the first and second outer spacer portions of the dielectric liner, and the gate dielectric layer includes vertically extending portions formed on the first and second outer spacer portions of the dielectric liner, the vertically extending portions of the gate dielectric layer being positioned between the vertically extending sidewalls of the gate electrode and the first and second outer spacer portions of the dielectric liner; and

an interlevel dielectric layer extending over the first and second liner portions of the dielectric liner.

2. The nanosheet field-effect transistor device of claim 1, wherein the nanosheet channel layers have widths between ten and one hundred nanometers.

3. The nanosheet field-effect transistor device of claim 1, wherein the dielectric liner consists essentially of SiCO.

4. The nanosheet field-effect transistor device of claim 1, further including a dielectric inner spacer extending between each of the nanosheet channel layers and positioned between the all-around gate stacks and the source/drain regions, wherein the dielectric inner spacer and the dielectric liner consist essentially of the same material.

5. The nanosheet field-effect transistor device of claim 4, further including:

a semiconductor substrate;

an oxide layer on the semiconductor substrate, the vertical stack of nanosheet channel layers extending vertically from the oxide layer,

wherein the dielectric liner includes horizontal portions on the oxide layer.

6. The nanosheet field-effect transistor device of claim 5, wherein the dielectric inner spacer and the dielectric liner consist essentially of SiCO.

7. The nanosheet field-effect transistor device of claim 4, further including a dielectric inner spacer extending between each of the nanosheet channel layers and positioned between the all-around gate stacks and the source/drain regions, wherein the dielectric inner spacer comprises silicon dioxide and the dielectric liner consists essentially of SiCO.

8. The nanosheet field-effect transistor device of claim 1 wherein the interlevel dielectric layer extends over the first and second outer spacer portions.

9. The nanosheet field-effect transistor device of claim 8, wherein the nanosheet channel layers consist essentially of monocrystalline silicon.