Semiconductor device

• US 10,727,349 B2
• Filed: 05/30/2019
• Issued: 07/28/2020
• Est. Priority Date: 03/03/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sung Soo, Roh, Dong Hyun, Ryu, Koung Min, Hyun, Sang Jin
• Primary Examiner(s): Fernandes, Errol V
• Application Number:
  US16/426,819
• Publication Number:
  US 20190280116A1
• Time in Patent Office: 425 Days
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes an active fin on a substrate, a device isolation film covering a lower portion of the active fin, a gate structure covering the active fin and the device isolation film, and a gate spacer on a side wall of the gate structure, wherein a side wall of the gate structure disposed on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate structure to a bottom of the gate structure, and an inner side wall of the gate spacer on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate spacer to a bottom of the gate spacer while forming an acute angle with a bottom surface of the gate spacer.

Claims

1. A semiconductor device, comprising:

active fins on a substrate;

an isolation film between the active fins;

a gate structure including a first gate portions on the active fins and a second gate portion on the isolation film;

a source/drain region adjacent to the gate structure, the source/drain region including a plurality of source/drain portions on the active fins and a merged portion on the isolation film and between the plurality of source/drain portions;

an interposed region between the merged portion and the isolation film;

a preliminary region on the merged portion; and

a gate spacer on a sidewall of the gate structure,

wherein the gate spacer includes a first spacer portion between the interposed region and the gate structure, a second spacer portion between the merged portion and the gate structure, and a third spacer portion between the preliminary region and the gate structure,

wherein a width of at least a portion of the first spacer portion is greater than a width of at least a portion of the second spacer portion, and

wherein a width of at least a portion of the second spacer portion is greater than a width of at least of the third spacer portion.

2. The semiconductor device of claim 1, wherein the gate spacer includes a first spacer layer adjacent to the gate structure and a second spacer layer disposed on an outer side wall of the first spacer layer.

3. The semiconductor device of claim 2, wherein a width of at least a portion of the second spacer layer on the isolation film increases toward the isolation film.

4. The semiconductor device of claim 3, wherein the first spacer layer has a structure bent at a boundary of the gate structure and the isolation film.

5. The semiconductor device of claim 2, wherein a width of at least a portion of the first spacer layer on the isolation film increases toward the isolation film.

6. The semiconductor device of claim 1, wherein at least a portion of a sidewall of the gate structure forms an acute angle with a top surface of the gate structure.

7. The semiconductor device of claim 1, wherein second spacer portion is continuously extended from the first spacer portion, and

wherein the third spacer portion is continuously extended from the second spacer portion.

8. The semiconductor device of claim 1, wherein the interposed region includes a void.

17. The semiconductor device of claim 1, wherein the gate structure includes a gate electrode layer and a gate insulating layer,

wherein the gate insulating layer includes a first gate insulating portion covering a bottom surface of the gate electrode layer, and a second gate insulating portion extending from the first gate insulating portion and covering a side wall of the gate electrode layer,

wherein the second gate insulating portion is between the gate spacer and the side wall of the gate electrode layer, and

wherein a width of at least a portion of the gate electrode layer overlapping the isolation film continuously increases toward the isolation film.

9. A semiconductor device comprising:

active fins on a substrate;

an isolation film between the active fins;

a gate structure on the active fins and the isolation film; and

a gate spacer on a side wall of the gate structure,

wherein the gate structure includes a gate electrode layer and a gate insulating layer,

wherein the gate insulating layer includes a first gate insulating portion covering a bottom surface of the gate electrode layer, and a second gate insulating portion extending from the first gate insulating portion and covering a side wall of the gate electrode layer,

wherein the second gate insulating portion is between the gate spacer and the side wall of the gate electrode layer,

wherein the gate spacer includes a first spacer layer and a second spacer layer,

wherein the first spacer layer includes a side portion between the second spacer layer and the side wall of the gate structure, and a bottom portion extending from the side portion and covering a bottom surface of the second spacer layer,

wherein the second spacer layer includes a lower portion including the bottom surface of the second spacer layer, an upper portion including a top surface of the second spacer layer, and a middle portion between the lower portion and the upper portion, and

wherein a width of at least a portion of the lower portion of the second spacer layer continuously increases toward the isolation film.

10. The semiconductor device of claim 9, wherein a width of the gate spacer increases toward an upper surface of the substrate, and wherein the width is widest at a portion in which the gate spacer is in contact with the isolation film.

11. The semiconductor device of claim 9, further comprising:

a source/drain region including source/drain portions protruding from the active fins adjacent to the gate structure and a merged portion extending from the source/drain portions; and

a void between the merged portion and the isolation film.

12. The semiconductor device of claim 9, wherein a side wall of the gate structure disposed on the isolation film is inclined at a uniform inclination from a point higher than half of a height of the gate structure to a bottom of the gate structure.

13. The semiconductor device of claim 9, wherein a width of a lower portion of the gate spacer overlapping the isolation film in a vertical direction is greater than a width of a lower portion of the gate spacer overlapping the active fins in the vertical direction, and

wherein the vertical direction is perpendicular to an upper surface of the substrate.

18. The semiconductor device of claim 9, wherein a width of at least a portion of the lower portion of the second spacer layer is greater than a width of at least a portion of the middle portion of the second spacer layer, and

wherein a width of at least a portion of the middle portion of the second spacer layer is greater than a width of at least a portion of the upper portion of the second spacer layer.

14. A semiconductor device comprising:

a first active fin on a substrate;

an isolation film adjacent to the first active fin on the substrate;

a gate structure on the first active fin and the isolation film; and

a gate spacer on a side wall of the gate structure,

wherein the gate structure includes a gate electrode layer and a gate insulating layer,

wherein the gate insulating layer includes a first gate insulating portion covering a bottom surface of the gate electrode layer, and a second gate insulating portion covering a side wall of the gate electrode layer,

wherein the second gate insulating portion is between the gate spacer and the side wall of the gate electrode layer,

wherein the gate spacer includes a first portion overlapping the isolation film and a second portion overlapping the first active fin in a vertical direction,

wherein the vertical direction is perpendicular to an upper surface of the substrate,

wherein the first portion of the gate spacer includes a first lower portion including a bottom surface of the first portion, a first upper portion including a top surface of the first portion, and a first middle portion between the first lower portion and the first upper portion,

wherein the second portion of the gate spacer includes a second lower portion including a bottom surface of the second portion, a second upper portion including a top surface of the second portion, and a second middle portion between the second lower portion and the second upper portion,

wherein a width of the first lower portion of the gate spacer continuously increases toward the isolation film, and

wherein a width of the first lower portion of the gate spacer is greater than a width of the second lower portion of the gate spacer.

15. The semiconductor device of claim 14, further comprising:

a second active fin on the substrate; and

a source/drain region including a first source/drain portion, a second source/drain portion, and a merged portion extending from the first source/drain portion and the second source/drain portion,

wherein the isolation film is between the first active fin and the second active fin,

wherein the first source/drain portion protrudes from the first active fin adjacent to the gate structure, and

wherein the second source/drain portion protrudes from the second active fin adjacent to the gate structure.

16. The semiconductor device of claim 14, wherein the gate spacer includes a first spacer layer adjacent to the gate structure, and a second spacer layer on an outer side wall of the first spacer layer, and

wherein at least one of the first spacer layer and the second spacer layer increases toward the isolation film.

19. The semiconductor device of claim 14, wherein a width of at least a portion of the first lower portion is greater than a width of at least a portion of the first middle portion, and

wherein a width of at least a portion of the first middle portion is greater than a width of at least a portion of the first upper portion.

20. The semiconductor device of claim 14, wherein a width of a bottom surface of the first lower portion of the gate spacer is greater than a width of a bottom surface of the second lower portion of the gate spacer.