Semiconductor device and manufacturing method of the same

• US 10,727,355 B2
• Filed: 03/03/2016
• Issued: 07/28/2020
• Est. Priority Date: 03/06/2015
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Kim, Jay C
• Application Number:
  US15/059,830
• Publication Number:
  US 20160260838A1
• Time in Patent Office: 1,608 Days
• Field of Search: 257 43
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes first and second insulators over a substrate, a semiconductor over the second insulator, first and second conductors over the semiconductor, a third insulator over the semiconductor, a fourth insulator over the third insulator, a third conductor over the fourth insulator, and a fifth insulator over the first insulator, the first conductor and the second conductor. The semiconductor includes first, second, and third regions. The first region overlaps with the third conductor with the third insulator and the fourth insulator positioned therebetween. The second region overlaps with the third conductor with the first conductor, the fourth insulator, and the fifth insulator positioned therebetween. The third region overlaps with the third conductor with the second conductor, the fourth insulator, and the fifth insulator positioned therebetween. The fourth insulator is in contact with a side surface of the fifth insulator in a region overlapping with the semiconductor.

Claims

1. A semiconductor device comprising:

a first insulator over a substrate;

a second insulator over the first insulator;

a semiconductor over the second insulator, the semiconductor including a first region, a second region, and a third region, wherein the first region is located between the second region and the third region;

a source electrode and a drain electrode over the second region and the third region of the semiconductor, respectively;

a third insulator over and in contact with the first region of the semiconductor;

a fourth insulator over the source electrode and the drain electrode;

a first gate insulator including a first region over a top surface of the third insulator and a second region over and in contact with a side surface of the fourth insulator; and

a first gate electrode over the first gate insulator,

wherein an entirety of the third insulator is directly underneath the first gate electrode,

wherein the first insulator has a first region in contact with the second insulator and a second region in contact with one of the source electrode and the drain electrode, and

wherein a thickness of the first region of the first insulator is larger than a thickness of the second region of the first insulator.

2. The semiconductor device according to claim 1, wherein the third insulator has a stacked-layer structure including at least a first layer and a second layer.

3. The semiconductor device according to claim 1, wherein the semiconductor includes a first oxide semiconductor.

4. The semiconductor device according to claim 1, wherein the semiconductor includes a first oxide semiconductor having a c-axis aligned crystal part.

5. The semiconductor device according to claim 1, wherein each of the source electrode and the drain electrode has a stacked-layer structure including a plurality of layers.

6. The semiconductor device according to claim 1, wherein each of the source electrode and the drain electrode includes regions with different thicknesses.

7. The semiconductor device according to claim 1, further comprising a second gate electrode under the first insulator.

8. The semiconductor device according to claim 1, wherein each of the second insulator and the third insulator contains at least one element contained in the semiconductor.

9. The semiconductor device according to claim 1, wherein the semiconductor has electron affinity higher than the second insulator and the third insulator.