Multi-level cell programming using optimized multiphase mapping with balanced Gray code

• US 10,734,071 B2
• Filed: 12/13/2018
• Issued: 08/04/2020
• Est. Priority Date: 12/13/2018
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: El Gamal, Mostafa, Ravindran, Niranjay, Fitzpatrick, James
• Primary Examiner(s): Alrobaie, Khamdan N.
• Application Number:
  US16/219,825
• Publication Number:
  US 20200194063A1
• Time in Patent Office: 600 Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2211/562 Multilevel memory programming aspects
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: H03K 23/005 using minimum change code, e.g. Gray Code

Abstract

Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.

Claims

1. A data storage device, comprising:

a flash memory comprising memory cells; and

a controller configured to;

program, in a first phase, a first portion of data into the memory cells in a first-level cell mode;

read, from the memory cells, the programmed first portion of the data; and

program, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode,

wherein the mapping is based on minimizing an average voltage change of the memory cells from the first phase to the second phase while maintaining a balanced Gray code for memory pages in the second-level cell mode, wherein a difference between transition counts of any two pages of the memory pages does not exceed a predetermined transition count difference, wherein a sum of the transition counts for all of the memory pages does not exceed a maximum number of programming levels in the second-level cell mode,

wherein for the first phase, the controller is configured to program the first portion of the data into the memory cells in the first-level cell mode, to provide a first set of significant bits for two pages of the memory cells, across a first voltage distribution having a first plurality of states,

wherein for the second phase, the controller is configured to program the first portion of the memory cells in the second-level cell mode, to provide a second set of significant bits for two pages corresponding to the two pages associated with the first phase, across a second voltage distribution having a second plurality of states, based on the first set,

wherein a number of transition counts for each page of the two pages associated with the first phase is different from a number of transition counts for a corresponding page of the two pages associated with the second phase, and

wherein the predetermined transition count difference is 1.

2. The data storage device of claim 1, wherein a width of a state distribution in the memory cells in the first phase is different from a sum of widths of corresponding state distributions in the memory cells in the second phase according to the mapping.

3. The data storage device of claim 1, wherein widths of state distributions of the memory cells in the first phase are not uniform.

4. The data storage device of claim 1, wherein the sum of the transition counts equals the maximum number of programming levels in the second-level cell mode.

5. The data storage device of claim 4, wherein the controller is configured to read, from the memory cells, at least a subset of the programmed first portion of the data without using error correction.

6. The data storage device of claim 1, wherein the controller is configured to not store the first portion of data in a buffer separate from the memory cells.

7. The data storage device of claim 1, wherein the controller is configured to retrieve the mapping as a predetermined value stored in the data storage device.

8. The data storage device of claim 1, wherein minimizing the average voltage change comprises:

determining a total voltage change caused by the second phase with respect to all of the programming levels in the second-level cell mode;

dividing the total voltage change by the maximum number of programming levels in the second-level cell mode; and

determining that the divided total voltage satisfies a threshold voltage range.

9. The data storage device of claim 8, wherein determining the total voltage change comprises weighting at least one programming level of the programming levels.

10. The data storage device of claim 1, wherein the controller is configured to:

set the memory cells into the first-level cell mode, to configure the memory cells in the first-level cell mode to store a first number of bits per cell;

set the memory cells into the second-level cell mode, to configure the memory cells in the second-level cell mode to store a second number of bits per cell, wherein the second number of bits per cell is greater than the first number of bits per cell;

program the memory cells in the first-level cell mode to provide the first voltage distribution having a first maximum voltage; and

program the memory cells in the second-level cell mode to provide the second voltage distribution having a second maximum voltage,

wherein the second maximum voltage is greater than the first maximum voltage.

11. A method implemented using one or more controllers for one or more storage devices, the method comprising:

programming, in a first phase, a first portion of data into memory cells in a first-level cell mode;

reading, from the memory cells, the programmed first portion of the data;

programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode; and

determining the mapping based on minimizing an average voltage change of the memory cells from the first phase to the second phase while maintaining a balanced Gray code for memory pages in the second-level cell mode, wherein the maintaining comprises having transition counts between every two adjacent pages of the memory pages not exceeding a predetermined transition count difference,

wherein the programming, in the first phase, the first portion of data comprises programming the first portion of the data into the memory cells in the first-level cell mode, to provide a first set of significant bits for two pages of the memory cells, across a first voltage distribution having a first plurality of states,

wherein the second phase comprises programming the first portion of the memory cells in the second-level cell mode, to provide a second set of significant bits for two pages corresponding to the two pages associated with the first phase, across a second voltage distribution having a second plurality of states, based on the first set,

wherein a number of transition counts for each page of the two pages associated with the first phase is different from a number of transition counts for a corresponding page of the two pages associated with the second phase, and

wherein the predetermined transition count difference is 1.

12. The method of claim 11, wherein a width of a state distribution in the memory cells in the first phase is less than a sum of widths of corresponding state distributions in the memory cells in the second phase according to the mapping.

13. The method of claim 11, wherein programming the first portion of data does not store the first portion of data in a buffer separate from the memory cells.

14. The method of claim 13, wherein reading, from the memory cells, the programmed first portion of the data comprises reading at least a subset of the first portion of the data without using error correction.

15. The method of claim 11, wherein the average voltage change is weighted for at least one programmed state of the second-level cell mode.

16. A system, comprising:

means for programming, in a first phase, a first portion of data into memory cells in a multi-level cell (MLC) mode without writing to a buffer separate from the memory cells;

means for reading, from the memory cells, the programmed first portion of the data;

means for programming, in a second phase, a second portion of the data into the memory cells in a quad-level cell (QLC) mode, based on applying, to the read first portion of the data, a mapping from the MLC mode to the QLC mode; and

means for selecting the mapping from a plurality of candidate mappings based on means for minimizing an average voltage change of the mapping from the MLC mode to the QLC mode and means for maintaining a balanced Gray code for memory pages in the QLC mode,

wherein the means for programming, in the first phase, the first portion of the data comprises means for programming the first portion of the data into the memory cells in the MLC mode, to provide a first set of significant bits for two pages of the memory cells, across a first voltage distribution having a first plurality of states,

wherein the system comprises means for programming, in the second phase, the first portion of the memory cells in the QLC mode, to provide a second set of significant bits for two pages corresponding to the two pages associated with the first phase, across a second voltage distribution having a second plurality of states, based on the first set,

wherein a number of transition counts for each page of the two pages associated with the first phase is different from a number of transition counts for a corresponding page of the two pages associated with the second phase, and

wherein the means for maintaining the balanced Gray code comprises means for preventing transition counts between every two adjacent ones of the memory pages from exceeding a difference of 1.

17. The system of claim 16, wherein the means for maintaining the balanced Gray code means for providing a sum of the transition counts for all of the memory pages to equal 15.

18. The system of claim 16, wherein a width of a state distribution in the memory cells in the first phase is greater than a sum of widths of corresponding state distributions in the memory cells in the second phase according to the mapping.

19. The system of claim 16, wherein the means for reading, from the memory cells, the programmed first portion of the data is configured to read at least a subset of the first portion of data without using error correction.