Packaged integrated circuit having stacked die and method for therefor

• US 10,734,312 B2
• Filed: 07/18/2018
• Issued: 08/04/2020
• Est. Priority Date: 07/18/2018
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Carpenter, Burton Jesse, Gauen, Kim Roger
• Primary Examiner(s): Sabur, Alia
• Application Number:
  US16/038,684
• Publication Number:
  US 20200027823A1
• Time in Patent Office: 748 Days
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/27 Manufacturing methods
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83855 Hardening the adhesive by curing, i.e. thermosetting
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/62 : Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H04B 5/75 : for isolation purposes

Abstract

A packaged integrated circuit (IC) device includes a first set of stacked die having a first IC die, a first inductor in the first IC die, an isolation layer over the first IC die, a second IC die over the isolation layer, and a second inductor in the second IC die aligned to communicate with the first inductor, and a second set of stacked die having a third IC die, a third inductor in the third IC die, a second isolation layer over the third IC die, a fourth IC die over the second isolation layer, and a fourth inductor in the fourth IC die aligned to communicate with the third inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die, and the second isolation layer extends a second prespecified distance beyond a first edge of the fourth IC die.

Claims

1. A packaged integrated circuit (IC) device comprising:

a first set of stacked dies including;

a first IC die,

a first inductor in the first IC die,

an isolation layer over the first IC die,

a second IC die over the isolation layer, and

a second inductor in the second IC die aligned to communicate with the first inductor, wherein the isolation layer extends a prespecified distance beyond a first edge of the second IC die; and

a second set of stacked dies including;

a third IC die,

a third inductor in the third IC die,

a second isolation layer over the third IC die,

a fourth IC die over the second isolation layer, and

a fourth inductor in the fourth IC die aligned to communicate with the third inductor, wherein the second isolation layer extends a second prespecified distance beyond a first edge of the fourth IC die;

wherein the first IC die and the third IC die are coupled to receive high voltage signals as compared to voltage signals received by the second and fourth IC die, and wherein the packaged IC device further comprises at least one wire bond connected between the second IC die and the fourth IC die.

2. The packaged IC device of claim 1, further comprising:

a lead frame flag having a first section and a second section, wherein the first die is attached to the first section and the third die is attached to the second section, wherein the first and second section are physically separate from each other.

3. The packaged IC device of claim 2, further comprising:

an encapsulant over and surrounding the first set of stacked dies and the second set of stack dies, and between the first and second sections of the lead frame flag.

4. The packaged IC device of claim 1, wherein:

the first set includes a first adhesive layer between the first IC die and the isolation layer and a second adhesive layer between the isolation layer and the second IC die, and

the second set includes a third adhesive layer between the third IC die and the second isolation layer and a fourth adhesive layer between the second isolation layer and the fourth IC die.

5. The packaged IC device of claim 4, wherein the isolation layer includes a first material that is one of a group consisting of a dielectric, epoxy, bismaleimide triazine (BT), FR-4, a resin, and a polyimide material, and the second isolation layer includes a second material that is one of a group consisting of a dielectric, epoxy, bismaleimide triazine (BT), FR-4, a resin, and a polyimide material.

6. The packaged IC device of claim 1, wherein:

a first creepage distance between the first edge of the second IC die and a first edge of the insulator layer is at least 100 micrometers, and

a second creepage distance between the first edge of the fourth IC die and a first edge of the second insulator layer is at least 100 micrometers.

7. The packaged IC device of claim 1, wherein each lead of a first plurality of leads along a top edge of the packaged IC device is coupled to the first IC die or the third IC die.

8. The packaged IC device of claim 7, further comprising:

wire bonds to connect each lead of the first plurality of leads along the top edge of the packaged IC device to the first IC die or the third IC die.

9. The packaged IC device of claim 8, wherein each lead along a bottom edge, opposite the top edge, of the packaged IC device is coupled to the second IC die or the fourth IC device, and further comprising:

wire bonds to connect each lead of a second plurality of leads along the bottom edge of the packaged IC device to the second IC die or the fourth IC die.

10. The packaged IC device of claim 1, further comprising a leadless region between a first lead coupled to the first set of stacked dies and a second lead coupled to the second set of stacked dies, wherein the leadless region has a width greater than at least one pitch of leads adjacent one side of the leadless region.

11. A packaged integrated circuit (IC) device comprising:

a first set of stacked dies including;

a first IC die,

a first inductor in the first IC die,

an isolation layer over the first IC die,

a second IC die over the isolation layer, and

a second inductor in the second IC die aligned to communicate with the first inductor, wherein the isolation layer extends a prespecified distance beyond a first edge of the second IC die; and

a second set of stacked dies including;

a third IC die,

a third inductor in the third IC die,

a second isolation layer over the third IC die,

a fourth IC die over the second isolation layer, and

a fourth inductor in the fourth IC die aligned to communicate with the third inductor, wherein the second isolation layer extends a second prespecified distance beyond a first edge of the fourth IC die,

wherein the first IC die and third IC die are in separate high voltage domains, and the second IC die and the fourth IC die are in a separate low voltage domain, wherein each of the high voltage domains operate at higher voltages than the low voltage domain.

12. The packaged IC device of claim 11, further comprising:

a lead frame flag having a first section and a second section, wherein the first die is attached to the first section and the third die is attached to the second section, wherein the first and second section are physically separate from each other.

13. The packaged IC device of claim 12, further comprising:

an encapsulant over and surrounding the first set of stacked die and the second set of stack die, and between the first and second sections of the lead frame flag.

14. The packaged IC device of claim 11, wherein:

the first set includes a first adhesive layer between the first IC die and the isolation layer and a second adhesive layer between the isolation layer and the second IC die, and

the second set includes a third adhesive layer between the third IC die and the second isolation layer and a fourth adhesive layer between the second isolation layer and the fourth IC die.

15. The packaged IC device of claim 14, wherein the isolation layer includes a first material that is one of a group consisting of a dielectric, epoxy, bismaleimide triazine (BT), FR-4, a resin, and a polyimide material, and the second isolation layer includes a second material that is one of a group consisting of a dielectric, epoxy, bismaleimide triazine (BT), FR-4, a resin, and a polyimide material.

16. The packaged IC device of claim 11, wherein:

a first creepage distance between the first edge of the second IC die and a first edge of the insulator layer is at least 100 micrometers, and

a second creepage distance between the first edge of the fourth IC die and a first edge of the second insulator layer is at least 100 micrometers.

17. The packaged IC device of claim 11, wherein the first IC die and the third IC die are coupled to receive high voltage signals as compared to voltage signals received by the second and fourth IC die.

18. The packaged IC device of claim 17, wherein each lead along a top edge of the packaged IC device is coupled to the first IC die or the third IC die.

19. The packaged IC device of claim 17, further comprising a leadless region between a first lead coupled to the first set of stacked die and a second lead coupled to the second set of stacked die, wherein the leadless region has a width greater than at least one pitch of leads adjacent one side of the leadless region.

20. A packaged integrated circuit (IC) device comprising:

a first set of stacked die including;

a first IC die,

a first inductor in the first IC die,

an isolation layer over the first IC die,

a second IC die over the isolation layer,

a second inductor in the second IC die aligned to communicate with the first inductor, wherein the isolation layer extends a prespecified distance beyond a first edge of the second IC die, and

a conductive ring between isolation layer and the second IC die, the conducive ring extending past the first edge of the second IC die, wherein the first edge is perpendicular to the isolation layer; and

a second set of stacked die including;

a third IC die,

a third inductor in the third IC die,

a second isolation layer over the third IC die,

a fourth IC die over the second isolation layer, and

a fourth inductor in the fourth IC die aligned to communicate with the third inductor, wherein the second isolation layer extends a second prespecified distance beyond a first edge of the fourth IC die.