Methods, structures, and designs for self-aligning local interconnects used in integrated circuits

• US 10,734,383 B2
• Filed: 01/02/2018
• Issued: 08/04/2020
• Est. Priority Date: 10/26/2007
• Status: Active Grant

• Current Assignee: RPX Corporation
• Original Assignee: Tela Innovations, Inc.
• Inventors: Smayling, Michael C., Becker, Scott T.
• Primary Examiner(s): McCall-Shepard, Sonya D.
• Application Number:
  US15/860,046
• Publication Number:
  US 20180145075A1
• Time in Patent Office: 945 Days
• CPC Class Codes: G03F 1/62 Pellicles, e.g. pellicle assemblies, e.g. having membrane on support frame; Preparation thereof
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of linear-shaped conductive structures is defined to extend lengthwise in a first direction. Some of the plurality of linear-shaped conductive structures form one or more gate electrodes of corresponding transistor devices. A local interconnect conductive structure is formed between two of the plurality of linear-shaped conductive structures so as to extend in the first direction along the two of the plurality of linear-shaped conductive structures.

Claims

1. An integrated circuit, comprising:

a local interconnect conductive structure including a first portion and a second portion, the first portion of the local interconnect conductive structure having a substantially rectangular shape with a length measured in a first direction and a width measured in a second direction, the second portion of the local interconnect conductive structure having a substantially rectangular shape with a length measured in the second direction and a width measured in the first direction, the second portion of the local interconnect conductive structure connected to the first portion of the local interconnect conductive structure at a location in the second direction between neighboring gate electrode level conductive structures, wherein the first portion of the local interconnect structure is self-aligned between the neighboring gate electrode level conductive structures.

2. The integrated circuit as recited in claim 1, wherein the length of the first portion of the local interconnect conductive structure is greater than the width of the second portion of the local interconnect conductive structure.

3. The integrated circuit as recited in claim 1, wherein the length of the second portion of the local interconnect conductive structure is greater than the width of the first portion of the local interconnect conductive structure.

4. The integrated circuit as recited in claim 1, wherein the length of the first portion of the local interconnect conductive structure is greater than the width of the second portion of the local interconnect conductive structure, and wherein the length of the second portion of the local interconnect conductive structure is greater than the width of the first portion of the local interconnect conductive structure.

5. The integrated circuit as recited in claim 1, further comprising:

a contact conductive structure formed to physically contact the second portion of the local interconnect conductive structure.

6. The integrated circuit as recited in claim 5, wherein the first portion of the local interconnect conductive structure is not contacted by any contact conductive structure.

7. The integrated circuit as recited in claim 5, further comprising:

a first gate electrode level conductive structure having a substantially rectangular shape with a length measured in the first direction and a width measured in the second direction; and

a second gate electrode level conductive structure having a substantially rectangular shape with a length measured in the first direction and a width measured in the second direction,

wherein a first part of the first portion of the local interconnect conductive structure is positioned between the first gate electrode level conductive structure and the second gate electrode level conductive structure.

8. The integrated circuit as recited in claim 7, wherein the first part of the first portion of the local interconnect conductive structure is separated from the first gate electrode level conductive structure by a first distance as measured in the second direction, and wherein the first part of the first portion of the local interconnect conductive structure is separated from the second gate electrode level conductive structure by the first distance as measured in the second direction.

9. The integrated circuit as recited in claim 8, further comprising:

a third gate electrode level conductive structure having a substantially rectangular shape with a length measured in the first direction and a width measured in the second direction,

wherein a second part of the first portion of the local interconnect conductive structure is positioned between the first gate electrode level conductive structure and the third gate electrode level conductive structure.

10. The integrated circuit as recited in claim 9, wherein the second part of the first portion of the local interconnect conductive structure is separated from the first gate electrode level conductive structure by the first distance as measured in the second direction, and wherein the second part of the first portion of the local interconnect conductive structure is separated from the third gate electrode level conductive structure by the first distance as measured in the second direction.

11. The integrated circuit as recited in claim 10, wherein the second portion of the local interconnect conductive structure extends in the second direction between the second gate electrode level conductive structure and the third gate electrode level conductive structure.

12. The integrated circuit as recited in claim 11, wherein the contact conductive structure is not positioned between the second gate electrode level conductive structure and the third gate electrode level conductive structure.

13. The integrated circuit as recited in claim 12, wherein the second gate electrode level conductive structure is separated from the first gate electrode level conductive structure by a second distance as measured in the second direction, and wherein the third gate electrode level conductive structure is separated from the first gate electrode level conductive structure by the second distance as measured in the second direction.

14. The integrated circuit as recited in claim 13, further comprising:

a first diffusion region of a first diffusion type, wherein the first portion of the local interconnect conductive structure physically contacts the first diffusion region of the first diffusion type.

15. The integrated circuit as recited in claim 14, further comprising:

a first diffusion region of a second diffusion type, wherein the first portion of the local interconnect conductive structure physically contacts the first diffusion region of the second diffusion type.

16. The integrated circuit as recited in claim 15, wherein a first portion of the first gate electrode level conductive structure and the first diffusion region of the first diffusion type form parts of a transistor of a first transistor type.

17. The integrated circuit as recited in claim 16, wherein a second portion of the first gate electrode level conductive structure and the first diffusion region of the second diffusion type form parts of a transistor of a second transistor type.

18. The integrated circuit as recited in claim 17, further comprising:

a second diffusion region of the first diffusion type forming part of the first transistor of the first transistor type; and

a second diffusion region of the second diffusion type forming part of the first transistor of the second transistor type.

19. The integrated circuit as recited in claim 18, further comprising:

a first interconnect level conductive structure formed to physically connect with the contact conductive structure.

20. The integrated circuit as recited in claim 19, wherein the first interconnect level conductive structure has a substantially rectangular shape with a length measured in the second direction and a width measured in the first direction.

21. The integrated circuit as recited in claim 20, wherein the contact conductive structure formed to physically contact the second portion of the local interconnect conductive structure is a first contact conductive structure, the integrated circuit further comprising a second contact conductive structure formed to physically contact the first gate electrode level conductive structure.

22. The integrated circuit as recited in claim 21, wherein the second contact conductive structure is positioned to contact the first gate electrode level conductive structure at a location in the first direction between the transistor of the first transistor type and the transistor of the second transistor type.

23. The integrated circuit as recited in claim 22, further comprising:

a second interconnect level conductive structure formed to physically connect with the second contact conductive structure.

24. The integrated circuit as recited in claim 23, wherein the second interconnect level conductive structure has a substantially rectangular shape with a length measured in the second direction and a width measured in the first direction.

25. The integrated circuit as recited in claim 24, wherein the width of the second interconnect level conductive structure is substantially equal to the width of the first interconnect level conductive structure.