Nanosheet substrate to source/drain isolation

• US 10,734,523 B2
• Filed: 08/13/2018
• Issued: 08/04/2020
• Est. Priority Date: 08/13/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Lie, Fee Li, Ebrish, Mona, De Silva, Ekmini A., Seshadri, Indira, Karve, Gauri, Clevenger, Lawrence A., Clevenger, Leigh Anne H., Loubet, Nicolas
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Bowen, Adam S
• Application Number:
  US16/102,198
• Publication Number:
  US 20200052107A1
• Time in Patent Office: 722 Days
• Field of Search: 257401
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method of forming a nanosheet device is provided. The method includes forming a nanosheet channel layer stack and dummy gate structure on a substrate. The method further includes forming a curved recess in the substrate surface adjacent to the nanosheet channel layer stack. The method further includes depositing a protective layer on the curved recess, dummy gate structure, and exposed sidewall surfaces of the nanosheet layer stack, and removing a portion of the protective layer on the curved recess to form a downward-spiked ridge around the rim of the curved recess. The method further includes extending the curved recess deeper into the substrate to form an extended recess, and forming a sacrificial layer at the surface of the extended recess in the substrate.

Claims

1. A method of forming a nanosheet device, comprising:

forming a nanosheet channel layer stack and dummy gate structure on a substrate;

forming a curved recess in the substrate surface adjacent to the nanosheet channel layer stack;

depositing a protective layer on the curved recess, dummy gate structure, and exposed sidewall surfaces of the nanosheet layer stack;

removing a portion of the protective layer on the curved recess to form a downward-spiked ridge around the rim of the curved recess;

extending the curved recess deeper into the substrate to form an extended recess; and

forming a sacrificial layer at the surface of the extended recess in the substrate.

2. The method of claim 1, wherein the sacrificial layer is formed by oxidizing the portion of the substrate forming the surface of the extended recess.

3. The method of claim 1, wherein the sacrificial layer is formed by ion implantation into the portion of the substrate forming the surface of the extended recess.

4. The method of claim 1, further comprising removing the sacrificial layer from the surface of the extended recess to form an enlarged recess.

5. The method of claim 4, further comprising forming a second sacrificial layer at the surface of the enlarged recess.

6. The method of claim 5, wherein the second sacrificial layer is formed by oxidizing the portion of the substrate forming the surface of the enlarged recess.

7. The method of claim 5, wherein the second sacrificial layer is formed by ion implantation into the portion of the substrate forming the surface of the enlarged recess.

8. The method of claim 5, further comprising removing the second sacrificial layer from the surface of the enlarged recess to form an augmented recess.

9. The method of claim 8, wherein the augmented recess undercuts the nanosheet channel layer.

10. A method of forming a nanosheet device, comprising:

forming alternating separation layers and nanosheet channel layers on a substrate, and a dummy gate structure on the alternating separation layers and nanosheet channel layers;

forming a curved recess in the substrate surface adjacent to the nanosheet channel layer stack using a directional etch;

depositing a protective layer on the curved recess, dummy gate structure, and exposed sidewall surfaces of the nanosheet layer stack;

removing a portion of the protective layer on the curved recess to form a downward-spiked ridge around the rim of the curved recess;

extending the curved recess deeper into the substrate to form an extended recess;

forming a sacrificial layer at the surface of the extended recess in the substrate; and

removing the sacrificial layer from the surface of the extended recess to form an enlarged recess.

11. The method of claim 10, wherein the protective layer is made of a dielectric material selected from the group consisting of silicon oxycarbide (SiOC), silicon oxynitride (SiON), and the combination thereof.

12. The method of claim 11, wherein the nanosheet channel layers are silicon (Si) and the separation layers are silicon-germanium (SiGe).

13. The method of claim 12, wherein the sacrificial layer is formed by arsenic (As) implantation into the surface of the extended recess.

14. The method of claim 13, wherein the protective layer has a thickness in a range of about 1 nm to about 5 nm.

15. A nanosheet device, comprising:

one or more nanosheet channel layer segments on a support pillar formed by a substrate;

an active gate structure on the one or more nanosheet channel layer segments; and

an isolation fill layer having a rounded portion adjacent to an upper portion of the support pillar, wherein the isolation fill layer is in an augmented recess and on the sidewalls of the support pillar.

16. The nanosheet device of claim 15, further comprising source/drains on each of the one or more nanosheet channel layer segments, wherein a bottom source/drain closest to the support pillar is separated from the support pillar by the rounded portion of the isolation fill layer.

17. The nanosheet device of claim 16, further comprising an active gate structure on the nanosheet channel layer segments, wherein the active gate structure includes a gate dielectric layer on each of the one or more nanosheet channel layer segments and a conductive gate fill on the gate dielectric layer and between adjacent pairs of the one or more nanosheet channel layer segments.

18. The nanosheet device of claim 17, wherein the isolation fill layer is silicon nitride (SiN).

19. The nanosheet device of claim 17, wherein the augmented recess has a depth in a range of about 25 nm to about 60 nm.

20. The nanosheet device of claim 17, wherein the isolation fill layer has a thickness in a range of about 10 nm to about 40 nm on the sidewall of the support pillar.