Semiconductor device

• US 10,734,550 B2
• Filed: 08/24/2018
• Issued: 08/04/2020
• Est. Priority Date: 08/25/2017
• Status: Active Grant

• Current Assignee: Suzhou Lekin Semiconductor Company Limited
• Original Assignee: LG Innotek Company Limited (LG Corporation)
• Inventors: Sung, Youn Joon, Choi, Rak Jun
• Primary Examiner(s): Rizkallah, Kimberly N
• Assistant Examiner(s): Belousov, Alexander
• Application Number:
  US16/111,978
• Publication Number:
  US 20190067524A1
• Time in Patent Office: 711 Days
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/325 characterised by the doping materials
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/40 Materials therefor
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

Disclosed herein is a semiconductor device including: a semiconductor structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first insulating layer disposed on the semiconductor structure; a first electrode disposed on the first conductive semiconductor layer through a first hole of the first insulating layer; a second electrode disposed on the second conductive semiconductor layer through a second hole of the first insulating layer; a first cover electrode disposed on the first electrode; and a second cover electrode disposed on the second electrode, wherein the second cover electrode includes a plurality of pads, and a connecting portion configured to connect the plurality of pads, a width of the connecting portion is smallest at a central position between the adjacent pads, and an area ratio between the second cover electrode and the first cover electrode is in the range of 1:1.1 to 1:1.5.

Claims

1. A semiconductor device comprising:

a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer interposed between the first semiconductor layer and the second semiconductor layer;

a first electrode disposed on the first semiconductor layer;

a second electrode disposed on the second semiconductor layer;

a first cover electrode disposed on the first electrode; and

a second cover electrode disposed on the second electrode,

wherein;

the second cover electrode includes a plurality of pads, and connecting portions configured to connect the plurality of pads, and

a width of each of the connecting portions is smallest at a central position between the adjacent pads,

wherein the first electrode includes a first groove provided on an upper surface of the first electrode, and a protrusion configured to surround the first groove, and

wherein the first cover electrode is provided on the first groove and the protrusion.

2. The semiconductor device of claim 1, further comprising:

a first insulating layer disposed on the semiconductor structure; and

a second insulating layer disposed on the first cover electrode and the second cover electrode,

wherein

the first insulating layer includes a first hole in which the first electrode is disposed and a second hole in which the second electrode is disposed, and

the second insulating layer includes a third hole through which a part of the first cover electrode is exposed and a fourth hole through which a part of the second cover electrode is exposed.

3. The semiconductor device of claim 1, wherein the semiconductor structure includes:

a non-light emitting region in which the first semiconductor layer is exposed; and

a light emitting region including the active layer and the second semiconductor layer.

4. The semiconductor device of claim 2, wherein:

the semiconductor structure includes a plurality of divided regions defined by a first virtual line passing through centers of a first side surface and a third side surface and a second virtual line passing through centers of a second side surface and a fourth side surface;

the plurality of divided regions includes a first divided region having a first side surface and a fourth side surface, a second divided region having the first side surface and a second side surface, a third divided region having the second side surface and a third side surface, and a fourth divided region having the third side surface and the fourth side surface;

the plurality of pads include a first pad disposed in the first divided region, a second pad disposed in the second divided region, and a third pad disposed in the fourth divided region; and

the connecting portions include a first connecting portion configured to connect the first pad and the second pad, and a second connecting portion configured to connect the first pad and the third pad.

5. The semiconductor device of claim 4, wherein:

a width of the first connecting portion decreases as the first connecting portion is closer to the first virtual line; and

a width of the second connecting portion decreases as the second connecting portion is closer to the second virtual line.

6. The semiconductor device of claim 4, wherein the third hole is disposed in the third divided region.

7. The semiconductor device of claim 6, wherein the fourth hole has a shape corresponding to that of the second cover electrode.

8. The semiconductor device of claim 7, further comprising:

a plurality of first bump electrodes disposed on the first cover electrode via the third hole; and

a second bump electrode disposed on the second cover electrode via the fourth hole,

wherein the plurality of first bump electrodes are disposed on the pads of the second cover electrode.

9. The semiconductor device of claim 7, wherein a ratio between an area of the first cover electrode exposed through the third hole and an area of the second cover electrode exposed through the fourth hole is in a range of 1:

2 to 1;

5.

10. The semiconductor device of claim 4, wherein a ratio between an area of the first divided region and an area of the second cover electrode disposed in the first divided region is in a range of 1:

0.2 to 1;

0.5.

11. The semiconductor device of claim 1, further comprising an oxide film interposed between the protrusion and the first cover electrode.

12. The semiconductor device of claim 1, wherein:

the first cover electrode includes a first irregularity disposed in the first groove, and a second irregularity disposed in a spacer between the first insulating layer and the first electrode; and

the second irregularity is in contact with the first semiconductor layer.

13. The semiconductor device of claim 1, wherein the first cover electrode extends onto the first insulating layer.

14. The semiconductor device of claim 1, wherein the active layer generates light of an ultraviolet light wavelength band.

15. The semiconductor device of claim 1, wherein an area ratio between the second cover electrode and the first cover electrode is in a range of 1:

1.1 to 1;

1.5.