Complementary self-limiting logic

• US 10,734,998 B1
• Filed: 05/31/2019
• Issued: 08/04/2020
• Est. Priority Date: 05/31/2019
• Status: Active Grant

• Current Assignee: The Boeing Co.
• Original Assignee: The Boeing Co.
• Inventors: Cabanas-Holmen, Manuel, Maharrey, Jeff, Rabaa, Salim
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US16/428,697
• Time in Patent Office: 431 Days
• CPC Class Codes: H03K 17/163 Soft switching
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/0033 Radiation hardening
• CPC Class Codes: H03K 19/00338 In field effect transistor circuits
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 19/007 Fail-safe circuits
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

Systems, methods, and apparatus for complementary self-limiting logic are disclosed. In one or more embodiments, a method for mitigating errors caused by transients in a logic gate transistor comprises biasing, by a first stage of transistors, a second stage of transistors such that a voltage potential across terminals of each of the transistors of the second stage are at an equal voltage potential. The method further comprises biasing, by the second stage of transistors, the logic gate transistor such that a voltage potential across terminals of the logic gate transistor are at an equal voltage potential, thereby ensuring that the transients will not cause the logic gate transistor to erroneously change logic states when the logic gate transistor is in a logically off state.

Claims

1. A method for mitigating errors caused by transients in a logic gate transistor, the method comprising:

biasing, by a first stage of transistors, a second stage of transistors such that a voltage potential across terminals of each of the transistors of the second stage are at an equal voltage potential; and

biasing, by the second stage of transistors, the logic gate transistor such that a Voltage potential across terminals of the logic gate transistor are at an equal voltage potential, thereby ensuring that the transients will not cause the logic gate transistor to erroneously change logic states when the logic gate transistor is in a logically off state.

2. The method of claim 1, wherein the transients are due to one of a radiation event, a noise event, or crosstalk.

3. The method of claim 1, wherein the logic gate transistor is a field-effect transistor (FET).

4. The method of claim 3, wherein the FET is one of a metal-oxide-semiconductor field-effect transistor (MOSFET) or a junction field-effect transistor (JFET).

5. The method of claim 1, wherein the logic gate transistor is one of a p-type transistor or an n-type transistor.

6. The method of claim 1, wherein the terminals of the logic gate transistor are a source terminal and a drain terminal.

7. The method of claim 1, wherein the transistors of the first stage of transistors comprise a p-type transistor and an n-type transistor.

8. The method of claim 1, wherein the transistors of the second stage of transistors comprise a p-type transistor and an n-type transistor.

9. The method of claim 1, wherein a system-on-a chip (SoC) device comprises the logic gate transistor, the first stage of transistors, and the second stage of transistors.

10. The method of claim 1, wherein a logic device comprises the logic gate transistor.

11. The method of claim 10, wherein the logic device is one of an inverter, an OR gate, a NOR gate, an AND gate, a NAND gate, a NOT gate, a XOR gate, or a XNOR gate.

12. A system for mitigating errors caused by transients in a logic gate transistor, the system comprising:

the logic gate transistor;

a first stage of transistors to bias a second stage of transistors such that a voltage potential across terminals of each of the transistors of the second stage are at an equal voltage potential; and

the second stage of transistors to bias the logic gate transistor such that a voltage potential across terminals of the logic gate transistor are at an equal voltage potential, thereby ensuring that the transients will not cause the logic gate transistor to erroneously change logic states when the logic gate transistor is in a logically off state.

13. The system of claim 12, wherein the transients are due to one of a radiation event, a noise event, or crosstalk.

14. The system of claim 12, wherein the logic gate transistor is a field-effect transistor (FET).

15. The system of claim 14, wherein the FET is one of a metal-oxide-semiconductor field-effect transistor (MOSFET) or a junction field-effect transistor (JFET).

16. The system of claim 12, wherein the logic gate transistor is one of a p-type transistor or an n-type transistor.

17. The system of claim 12, wherein the terminals of the logic gate transistor are a source terminal and a drain terminal.

18. The system of claim 12, wherein the system is a system-on-a-chip (SoC) device.

19. The system of claim 12, wherein a logic device comprises the system.

20. The system of claim 19, wherein the logic device is one of an inverter, an OR gate, a NOR gate, an AND gate, a NAND gate, a NOT gate, a XOR gate, or a XNOR gate.