Fin field effect transistor (FinFET) device structure and method for forming the same

• US 10,741,408 B2
• Filed: 04/15/2019
• Issued: 08/11/2020
• Est. Priority Date: 07/02/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chang-Yin, Chang, Chai-Wei, Liao, Chia-Yang, Young, Bo-Feng
• Primary Examiner(s): Kraig, William F
• Assistant Examiner(s): Rahman, Khatib A
• Application Number:
  US16/384,491
• Publication Number:
  US 20190244830A1
• Time in Patent Office: 484 Days
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence

Abstract

A FinFET device structure and method for forming the same are provided. The fin field effect transistor (FinFET) device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure. The upper portion has a top surface with a first width, the lower portion has a bottom surface with a second width, and the first width is greater than the second width.

Claims

1. A method for forming a fin field effect transistor (FinFET) device structure, comprising:

forming a fin structure extending away from an isolation region over a semiconductor substrate, the fin structure comprising a top surface facing away from the semiconductor substrate;

depositing a dummy material over the fin structure;

patterning the fin structure to form a dummy gate structure, the dummy gate structure comprising a vertical upper portion above the top surface and a notched lower portion below the top surface, the upper portion having a first width that is greater than a second width of the lower portion, the lower portion also having a third width that is less than the second width;

forming spacers adjacent to the dummy gate structure;

depositing an interlayer dielectric adjacent to the dummy gate structure; and

replacing the dummy gate structure with a gate dielectric and a gate electrode.

2. The method of claim 1, wherein the fin structure has a width that increases from a top portion of the fin structure to a bottom portion of the fin structure.

3. The method of claim 1, wherein the lower portion has sloped sidewalls.

4. The method of claim 1, wherein the lower portion has a trapezoidal shape.

5. The method of claim 1, wherein a difference between the first width and the second width is less than about 15 nm.

6. The method of claim 1, wherein an interface between the upper portion and the lower portion is substantially level with a top surface of the fin structure.

7. The method of claim 1, wherein the upper portion has a first height and the lower portion has a second height that is less than the first height.

8. A method for forming a fin field effect transistor (FinFET) device structure, comprising:

etching a dummy material over a semiconductor fin to form a dummy gate structure, the dummy gate structure having a first width located a first distance away from a semiconductor substrate, a second width located a second distance away from the semiconductor substrate, and a third width located a third distance away from the semiconductor substrate, the second distance being greater than the first distance and the second width being less than the first width, the third distance being greater than the second distance and the third width being greater than the second width;

forming dielectric materials around the dummy gate structure;

planarizing the dielectric materials to expose the dummy gate structure; and

removing the dummy gate structure.

9. The method of claim 8, wherein the dummy gate structure has a top portion at least partially at the first distance and a bottom portion at least partially at the second distance, wherein the top portion has a constant width and the bottom portion has a varied width.

10. The method of claim 8, wherein the dummy gate structure has a top portion at least partially at the first distance and a bottom portion at least partially at the second distance, wherein the top portion has a first height and the bottom portion has a second height less than the first height.

11. The method of claim 8, wherein the dummy gate structure extends over a second semiconductor fin.

12. The method of claim 11, wherein the dummy gate structure extends over a third semiconductor fin and a fourth semiconductor fin.

13. The method of claim 8, wherein the etching the dummy material over the semiconductor fin forms a second dummy gate structure.

14. The method of claim 13, wherein the second dummy gate structure has a fourth width located a fourth distance away from the semiconductor substrate, a fifth width located a fifth distance away from the semiconductor substrate, and a sixth width located a sixth distance away from the semiconductor substrate, the fifth distance being greater than the fourth distance and the fifth width being less than the fourth width, the sixth distance being greater than the fifth distance and the sixth width being greater than the fifth width.

15. A method for forming a fin field effect transistor (FinFET) device structure, comprising:

forming a spacer adjacent to a dummy gate structure over a semiconductor fin, wherein the forming the spacer forms a first vertical portion, a first angled portion, and a first horizontal portion extending between the first vertical portion and the first angled portion, the dummy gate structure having a first width located a first distance away from a semiconductor substrate, a second width located a second distance away from the semiconductor substrate, and a third width located a third distance away from the semiconductor substrate, the second distance being greater than the first distance and the second width being less than the first width, the third distance being greater than the second distance and the third width being greater than the second width;

depositing an interlayer dielectric around the spacer and the dummy gate structure;

removing the dummy gate structure to form an opening, the opening having the spacer as a sidewall; and

depositing a gate electrode within the opening.

16. The method of claim 15, wherein the spacer has a second vertical portion, a second angled portion, and a second horizontal portion extending between the second vertical portion and the second angled portion.

17. The method of claim 15, wherein the forming the spacer further comprises patterning a dummy material to form the dummy gate structure.

18. The method of claim 17, wherein the patterning the dummy material is performed utilizing a plasma process with HBr.

19. The method of claim 18, wherein the plasma process is performed at a power in a range from about 350 Watt to about 1500 Watt.

20. The method of claim 19, wherein the plasma process is performed at a pressure in a range from about 10 torr to about 100 torr.