Transistor array panel and manufacturing method thereof

• US 10,741,586 B2
• Filed: 07/18/2019
• Issued: 08/11/2020
• Est. Priority Date: 12/19/2016
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kim, Tae Gyun, Ka, Jae-Yong, Hong, Pil Soon
• Primary Examiner(s): Malsawma, Lex H
• Assistant Examiner(s): Cross, Xia L
• Application Number:
  US16/516,149
• Publication Number:
  US 20190341405A1
• Time in Patent Office: 390 Days
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs

Abstract

A transistor array panel includes a transistor which includes a gate electrode, a semiconductor layer on the gate electrode, and a source electrode and a drain electrode on the semiconductor layer. The semiconductor layer includes a first portion overlapping the source electrode, a second portion overlapping the drain electrode, and a third portion between the first portion and the second portion. The first portion, the second portion, and the third portion have different minimum thicknesses.

Claims

1. A method for manufacturing a transistor array panel, comprising:

forming a gate electrode on a substrate;

forming a gate insulating layer to cover the gate electrode;

sequentially forming a semiconductor layer, a first ohmic contact layer, and a first conductive layer on the gate insulating layer;

patterning the first conductive layer, the first ohmic contact layer, and the semiconductor layer;

sequentially forming a second ohmic contact layer and a second conductive layer; and

patterning the second conductive layer and the second ohmic contact layer,

wherein the patterning steps are conducted to form the semiconductor layer to include a first portion with a first thickness t1 between the first conductive layer and the gate electrode, a second portion with a second thickness t2 between the second conductive layer and the gate electrode, and a third portion with a third thickness t3 between the first portion and the second portion, and

wherein the second thickness t2 is less than the first thickness t1, and the third thickness t3 is less than the second thickness t2.

2. The method as claimed in claim 1, wherein patterning the first conductive layer includes:

forming a first-stage photosensitive film pattern including a first portion and a second portion with different thicknesses on the first conductive layer; and

etching the first conductive layer using the first-stage photosensitive film pattern as a mask.

3. The method as claimed in claim 2, wherein patterning the first ohmic contact layer and the semiconductor layer includes:

forming a second-stage photosensitive film pattern by etching back the first-stage photosensitive film pattern, and

etching the first ohmic contact layer and the semiconductor layer using the patterned first conductive layer as a mask.

4. The method as claimed in claim 3, further comprising:

after etching the semiconductor layer, etching the patterned first conductive layer using the second-stage photosensitive film pattern as a mask to form a source electrode or a drain electrode.

5. The method as claimed in claim 4, further comprising:

after the forming of the source electrode or the drain electrode, etching the patterned first ohmic contact layer using the second-stage photosensitive film pattern as a mask to form a first ohmic contact overlapping the source electrode or the drain electrode.

6. The method as claimed in claim 5, wherein patterning the second conductive layer and the second ohmic contact layer includes:

etching the second conductive layer using a photosensitive film pattern as a mask to form the drain electrode or the source electrode; and

etching the second ohmic contact layer using the photosensitive film pattern as a mask to form a second ohmic contact overlapping the drain electrode or the source electrode.

7. The method as claimed in claim 2, wherein patterning the first ohmic contact layer and the semiconductor layer includes:

etching the first ohmic contact layer and the semiconductor layer using the first-stage photosensitive film pattern as a mask.

8. The method as claimed in claim 7, further comprising after etching the semiconductor layer:

etching back the first-stage photosensitive film pattern to form a second-stage photosensitive film pattern, and

etching the patterned first conductive layer using the second-stage photosensitive film pattern as a mask to form a source electrode or a drain electrode.

9. The method as claimed in claim 8, further comprising after forming the source electrode or the drain electrode:

etching the patterned first ohmic contact layer using the second-stage photosensitive film pattern as a mask to form a first ohmic contact overlapping the source electrode or the drain electrode.

10. The method as claimed in claim 9, wherein patterning the second conductive layer and the second ohmic contact layer includes:

etching the second conductive layer using a photosensitive film pattern as a mask to form the drain electrode or the source electrode; and

etching the second ohmic contact layer using the photosensitive film pattern as a mask to form a second ohmic contact overlapping the drain electrode or the source electrode.