Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection

• US 10,741,639 B2
• Filed: 09/28/2018
• Issued: 08/11/2020
• Est. Priority Date: 09/28/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Loubet, Nicolas, Chao, Robin Hsin Kuo, Frougier, Julien, Xie, Ruilong
• Primary Examiner(s): Gupta, Raj R
• Application Number:
  US16/146,377
• Publication Number:
  US 20200105869A1
• Time in Patent Office: 683 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A technique relates to a semiconductor device. A stack is formed over a bottom sacrificial layer, the bottom sacrificial layer being on a substrate. At least a portion of the bottom sacrificial layer is removed so as to create openings. Inner spacers are formed in the openings adjacent to the bottom sacrificial layer. The bottom sacrificial layer is removed so as to create a void. An isolation layer formed on the inner spacers so as to form an air gap, the isolation layer and the air gap being positioned between the stack and the substrate.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a stack over a bottom sacrificial layer, the bottom sacrificial layer being on a substrate;

removing at least a portion of the bottom sacrificial layer so as to create openings;

forming inner spacers in the openings adjacent to the bottom sacrificial layer;

removing the bottom sacrificial layer so as to create a void;

forming an isolation layer on the inner spacers so as to form an air gap, the isolation layer and the air gap being positioned between the stack and the substrate; and

forming source and drain regions overlying both the isolation layer and the air gap having been formed by the isolation layer.

2. The method of claim 1, wherein removing the portion of the bottom sacrificial layer so as to create the openings comprises recessing sides of the bottom sacrificial layer.

3. The method of claim 2, wherein recessing the sides of the bottom sacrificial layer causes a width of the bottom sacrificial layer to be less than a width of the stack.

4. The method of claim 1, wherein the void is between the stack and the substrate.

5. The method of claim 1, wherein the void is between the inner spacers.

6. The method of claim 1, wherein the isolation layer and the air gap physically and electrically separate the source and drain regions from the substrate.

7. The method of claim 1, wherein:

the stack comprises a plurality of channel layers, each of the plurality of channels layers being separate from one another;

a conductive gate structure is formed on the plurality of channel layers; and

the isolation layer separates a bottom portion of the conductive gate structure from the substrate.

8. The method of claim 1, wherein the isolation layer comprises a nitride.

9. The method of claim 1, wherein the isolation layer comprises silicon boron carbide nitride.

10. The method of claim 1, wherein:

source and drain regions are formed on the isolation layer and are operable to permit current flow via channel layers in the stack; and

the isolation layer is positioned to prevent current leakage from one of the source and drain regions to another one of the source and drain regions via the substrate.