Passive multi-input comparator for orthogonal codes on a multi-wire bus

• US 10,742,451 B2
• Filed: 06/07/2019
• Issued: 08/11/2020
• Est. Priority Date: 06/12/2018
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Tajalli, Armin, Cao, Chen, Gharibdoust, Kiarash
• Primary Examiner(s): Lee, Siu M
• Application Number:
  US16/435,412
• Publication Number:
  US 20190379563A1
• Time in Patent Office: 431 Days
• CPC Class Codes: H03M 5/14 Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
• CPC Class Codes: H03M 7/20 Conversion to or from n-out-of-m codes
• CPC Class Codes: H04B 3/02 Details
• CPC Class Codes: H04L 25/0274 Arrangements for ensuring balanced coupling
• CPC Class Codes: H04L 25/0276 Arrangements for coupling common mode signals
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 25/49 using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems spectral shaping H04L25/03828

Abstract

Methods and systems are described for receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code, generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, the plurality of output nodes including a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels, and generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.

Claims

1. An apparatus comprising:

a plurality of wires of a multi-wire bus configured to carry signals corresponding to symbols of a codeword of a vector signaling code;

an interconnected resistor network comprising a plurality of tunable resistors, the interconnected resistor network connected to the plurality of wires of the multi-wire bus, the interconnected resistor network configured to receive the signals corresponding to the symbols of the codeword of the vector signaling code and to responsively generate combinations of the symbols of the codeword of the vector signaling code at a plurality of output nodes, each output node of the plurality of output nodes connected to a respective two or more wires of the plurality of wires of the multi-wire bus via the plurality of tunable resistors, the plurality of output nodes grouped into a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels; and

a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes and configured to generate a respective sub-channel output of a plurality of sub-channel outputs.

2. The apparatus of claim 1, wherein each combination of the symbols of the codeword corresponds to an addition of a respective two symbols of the codeword.

3. The apparatus of claim 1, wherein each combination of the symbols of the codeword corresponds to an average of a respective two symbols of the codeword.

4. The apparatus of claim 1, wherein the plurality of tunable resistors each have equal impedance values.

5. The apparatus of claim 1, wherein each tunable resistor of the plurality of tunable resistors comprises a parallel-resistor network configured to selectively enable one or more resistors in the parallel-resistor network to set a value of a tunable impedance of the tunable resistor.

6. The apparatus of claim 1, wherein the interconnected resistor network is configured to adjust a tunable impedance of each tunable resistor of the plurality of tunable resistors to adjust high-frequency peaking of sub-channel outputs of the interconnected resistor network.

7. The apparatus of claim 1, further comprising a plurality of mode-selection transistors configured to selectively decouple one or more wires from one or more output nodes of the plurality of output nodes.

8. The apparatus of claim 7, wherein the plurality of mode-selection transistors are configured to couple one respective wire of the plurality of wires of the multi-wire bus to a respective output node of the plurality of output nodes, and wherein each sub-channel output of the plurality of sub-channel outputs corresponds to a differential output across two wires of the plurality of wires of the multi-wire bus.

9. A method comprising:

receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code;

generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, each output node of the plurality of output nodes is connected to a respective two or more wires of the plurality of wires of the multi-wire bus, each wire of the respective two or more wires connected via a respective tunable resistor of a plurality of tunable resistors of the interconnected resistor network, the plurality of output nodes comprising a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels; and

generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.

10. The method of claim 9, wherein generating the plurality of combinations of the symbols of the codeword comprises adding a respective two or more signals corresponding to a respective two or more symbols of the codeword.

11. The method of claim 9, wherein generating the plurality of combinations of the symbols of the codeword comprises forming an average of a respective two or more signals corresponding to a respective two or more symbols of the codeword.

12. The method of claim 9, wherein the plurality of tunable resistors each have equal impedance values.

13. The method of claim 9, wherein each tunable resistor of the plurality of tunable resistors comprises a parallel-resistor network, and wherein the method further comprises selectively enabling one or more resistors in the parallel-resistor network to set an impedance value of a tunable impedance of the tunable resistor.

14. The method of claim 9, further comprising adjusting high-frequency peaking of the plurality of sub-channel outputs by adjusting tunable impedance of the plurality of tunable resistors.

15. The method of claim 9, further comprising selecting an operational mode via a plurality of mode-selection transistors, the plurality of mode-selection transistors selectively decoupling one or more wires from one or more output nodes of the plurality of output nodes.

16. The method of claim 15, further comprising coupling one respective wire of the plurality of wires of the multi-wire bus to a respective output node of the plurality of output nodes, and wherein each sub-channel output of the plurality of sub-channel outputs corresponds to a differential output across two wires of the plurality of wires of the multi-wire bus.