Passive multi-input comparator for orthogonal codes on a multi-wire bus
First Claim
1. An apparatus comprising:
- a plurality of wires of a multi-wire bus configured to carry signals corresponding to symbols of a codeword of a vector signaling code;
an interconnected resistor network comprising a plurality of tunable resistors, the interconnected resistor network connected to the plurality of wires of the multi-wire bus, the interconnected resistor network configured to receive the signals corresponding to the symbols of the codeword of the vector signaling code and to responsively generate combinations of the symbols of the codeword of the vector signaling code at a plurality of output nodes, each output node of the plurality of output nodes connected to a respective two or more wires of the plurality of wires of the multi-wire bus via the plurality of tunable resistors, the plurality of output nodes grouped into a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels; and
a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes and configured to generate a respective sub-channel output of a plurality of sub-channel outputs.
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Accused Products
Abstract
Methods and systems are described for receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code, generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, the plurality of output nodes including a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels, and generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes.
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Citations
16 Claims
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1. An apparatus comprising:
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a plurality of wires of a multi-wire bus configured to carry signals corresponding to symbols of a codeword of a vector signaling code; an interconnected resistor network comprising a plurality of tunable resistors, the interconnected resistor network connected to the plurality of wires of the multi-wire bus, the interconnected resistor network configured to receive the signals corresponding to the symbols of the codeword of the vector signaling code and to responsively generate combinations of the symbols of the codeword of the vector signaling code at a plurality of output nodes, each output node of the plurality of output nodes connected to a respective two or more wires of the plurality of wires of the multi-wire bus via the plurality of tunable resistors, the plurality of output nodes grouped into a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels; and a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes and configured to generate a respective sub-channel output of a plurality of sub-channel outputs. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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receiving a plurality of signals via a plurality of wires of a multi-wire bus, the plurality of signals corresponding to symbols of a codeword of a vector signaling code; generating, using an interconnected resistor network connected to the plurality of wires of the multi-wire bus, a plurality of combinations of the symbols of the codeword of the vector signaling code on a plurality of output nodes, each output node of the plurality of output nodes is connected to a respective two or more wires of the plurality of wires of the multi-wire bus, each wire of the respective two or more wires connected via a respective tunable resistor of a plurality of tunable resistors of the interconnected resistor network, the plurality of output nodes comprising a plurality of pairs of sub-channel output nodes associated with respective sub-channels of a plurality of sub-channels; and generating a plurality of sub-channel outputs using a plurality of differential transistor pairs, each differential transistor pair of the plurality of differential transistor pairs connected to a respective pair of sub-channel output nodes of the plurality of pairs of sub-channel output nodes. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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Specification