MOS-gated power device having extended trench and doping zone and process for forming same

• US 20010000919A1
• Filed: 11/30/2000
• Published: 05/10/2001
• Est. Priority Date: 05/19/1999
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Kocon, Christopher B.
• Application Number:
  US09/726,682
• Publication Number:
  US 20010000919A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench MOS-gated device comprises a doped monocrystalline semiconductor substrate that includes an upper layer and is of a first conduction type. An extended trench in the upper layer of the substrate has a bottom portion filled with a dielectric material that forms a thick layer in the bottom of the trench. The upper portion of the trench is lined with a dielectric material and substantially filled with a conductive material, the filled upper portion of the trench forming a gate region. An extended doped zone of a second opposite conduction type extends from the upper surface into the upper layer on one side of the trench, and a doped well region of the second conduction type overlying a drain zone of the first conduction type is disposed in the upper layer on the opposite side of the trench. The drain zone is substantially insulated from the extended zone by the thick dielectric layer in the bottom portion of the trench. A heavily doped source region of the first conduction type and a heavily doped body region of the second conduction type is disposed in the well region at the upper surface of the upper layer. An interlevel dielectric layer is disposed on the upper surface overlying the gate and source regions, and a metal layer overlying the upper surface and the interlevel dielectric layer is in electrical contact with the source and body regions and the extended zone. A process for constructing a trench MOS-gated device comprises forming an extended trench in an upper layer of a doped monocrystalline semiconductor substrate of a first conduction type, and substantially filling the trench with a dielectric material. A dopant of a second opposite conduction type is implanted and diffused into the upper layer on one side of the extended trench to form a doped extended zone extending into the upper layer from its upper surface. A selected portion of the dielectric material is removed from an upper portion of the trench, leaving a thick dielectric layer in its bottom portion. Sidewalls comprising dielectric material are formed in the upper portion of the trench, which is then substantially filled with a conductive material to form a gate region in the upper portion of the trench. A doped well region of the second conduction type is formed in the upper layer on the side of the trench opposite the doped extended zone. Heavily doped source and body regions are formed in the well region, and an interlevel dielectric layer is deposited on the upper surface overlying the gate and source regions. A metal layer in electrical contact with the source and body regions and the extended zone is formed over the substrate upper surface and the interlevel dielectric layer.

Claims

1. A trench MOS-gated device comprising:

a substrate including an upper layer, said substrate comprising doped monocrystalline semiconductor material of a first conduction type;

an extended trench in said upper layer, said trench having a bottom portion filled with a dielectric material, said material forming a thick dielectric layer in said bottom of said trench, said trench further having an upper portion lined with a dielectric material and substantially filled with a conductive material, said filled upper portion of said trench forming a gate region;

a doped extended zone of a second opposite conduction type extending from an upper surface into said upper layer on one side of said trench;

a doped well region of said second conduction type overlying a drain zone of said first conduction type in said upper layer on the opposite side of said trench, said drain zone being substantially insulated from said extended zone by said thick dielectric layer in said bottom portion of said trench;

a heavily doped source region of said first conduction type and a heavily doped body region of said second conduction type disposed in said well region at said upper surface;

an interlevel dielectric layer on said upper surface overlying said gate and source regions; and

a metal layer overlying said upper surface and said interlevel dielectric layer, said metal layer being in electrical contact with said source and body regions and said extended zone.

2. The device of

claim 1

further comprising:

a doped drain zone of said first conduction type extending beneath said well region and said extended zone.

3. The device of

claim 2

further comprising:

a heavily doped drain of said first conduction type disposed at a lower surface of said substrate and extending beneath said doped drain zone.

4. The device of

claim 1

wherein said doped extended zone extends into said upper layer to a depth substantially equal to the depth of the bottom of said trench.

5. The device of

claim 1

wherein said lower portion of said extended trench is narrowerer than said upper portion.

6. The device of

claim 1

wherein said upper layer is included in said substrate.

7. The device of

claim 1

wherein said upper layer is an epitaxial layer.

8. The device of

claim 1

wherein said substrate comprises monocrystalline silicon.

9. The device of

claim 1

wherein said dielectric material comprises silicon dioxide.

10. The device of

claim 1

wherein said conductive material in said trench comprises doped polysilicon.

11. The device of

claim 1

wherein said first conduction type is N and said second conduction type is P.

12. The device of

claim 1

wherein said device comprises a plurality of extended trenches.

13. The device of

claim 12

wherein said plurality of extended trenches have an open-cell stripe topology.

14. The device of

claim 12

wherein said plurality of extended trenches have a closed-cell cellular topology.

15. The device of

claim 1

selected from the group consisting of a power MOSFET, an insulated gate bipolar transistor, and an MOS-controlled thyristor.

16. A process for forming a trench MOS-gated device, said process comprising:

forming an extended trench in an upper layer of a substrate, said substrate comprising doped monocrystalline semiconductor material of a first conduction type;

substantially filling said extended trench with a dielectric material;

selectively implanting and diffusing a dopant of a second opposite conduction type into said upper layer on one side of said extended trench, thereby forming an extended zone extending from an upper surface into said upper layer;

removing a selected portion of said dielectric material from an upper portion of said trench, leaving a thick dielectric layer in a bottom portion of said trench;

forming sidewalls comprising dielectric material on the upper portion of said trench and substantially filling said upper portion with a conductive material, thereby forming a gate region in said upper portion of said trench;

forming a doped well region of said second conduction type in said upper layer on the side of said trench opposite said extended zone;

forming a heavily doped source region of said first conduction type and a heavily doped body region of said second conduction type in said well region at said upper surface;

forming an interlevel dielectric layer on said upper surface overlying said gate and source regions; and

forming a metal layer overlying said upper surface and said interlevel dielectric layer, said metal layer being in electrical contact with said source and body regions and said extended zone.

17. The process of

claim 16

further comprising:

forming a doped drain zone of said first conduction type extending beneath said well region and said extended zone.

18. The process of

claim 16

wherein said upper layer is included in said substrate.

19. The process of

claim 16

wherein said upper layer is an epitaxial layer.

20. The process of

claim 16

wherein said substrate comprises monocrystalline silicon.

21. The process of

claim 16

wherein said dielectric material comprises silicon dioxide.

22. The process of

claim 16

wherein said conductive material in said trench comprises doped polysilicon.

23. The process of

claim 16

wherein said first conduction type is N and said second conduction type is P.

24. The process of

claim 16

further comprising:

forming a plurality of extended trenches in said substrate.

25. The process of

claim 24

wherein said plurality of extended trenches have an open-cell stripe technology.

26. The process of

claim 24

wherein said plurality of extended trenches have a closed-cell cellular topology.

27. The process of

claim 16

wherein said device is selected from the group consisting of a power MOSFET, an insulated gate bipolar transistor, and an MOS-controlled thyristor.