Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners

• US 20010001215A1
• Filed: 12/28/2000
• Published: 05/17/2001
• Est. Priority Date: 10/29/1996
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Oleg Siniaguine, Patrick Halahan, Sergey Savastiouk
• Inventors: Halahan, Patrick, Savastiouk, Sergey, Siniaguine, Oleg
• Granted Patent: US 6,448,153 B2
• Time in Patent Office: Days
• US Class Current: 257/618
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/482 consisting of lead-in layers inseparably applied to the semiconductor body electrodes H01L29/40
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/10158 at the passive surface
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A semiconductor wafer is diced before thinning. The wafer is diced only part of the way through, to form grooves which are at least as deep as the final thickness of each chip to be obtained from the wafer. Then, the wafer is placed into a non-contact wafer holder, and the wafer backside is blanket etched with a dry etch, for example, atmospheric pressure plasma etch. The wafer is thinned until the grooves are exposed from the backside. The dry etch leaves the chip'"'"'s backside smooth. After the grooves have been exposed, the dry etch is continued to remove damage from the chip sidewalls and to round the chips'"'"' bottom edges and corners. As a result, the chip becomes more reliable, and in particular more resistant to thermal and other stresses.

Claims

1. A method for obtaining one or more chips from a semiconductor wafer, the method comprising:

forming one or more openings in a first surface of the semiconductor wafer along a boundary of the one or more chips, wherein the one or more openings do not go through the wafer; and

placing the wafer into a non-contact wafer holder and thinning the wafer with a dry etch to remove material from a second side of the wafer at least until the openings become exposed on the second side.

2. The method of

claim 1

wherein the one or more openings comprise a groove extending along the entire boundary of at least one chip.

3. The method of

claim 2

wherein the wafer holder comprises one or more vortex chucks each of which emits a gas vortex towards the wafer to hold the wafer in the holder.

4. The method of

claim 2

further comprising, after forming the one or more openings but before thinning the wafer, attaching the first side of the wafer to a layer which remains on the wafer while the wafer is thinned.

5. The method of

claim 2

further comprising, after forming the one or more openings, forming a protective layer on the first side over the openings, the protective layer protecting the first side of the wafer during the dry etch from an etchant penetrating through the openings from the second side and damaging the first side when the openings become exposed on the second side.

6. The method of

claim 5

wherein the layer does not cover the entire first side of the wafer.

7. The method of

claim 5

wherein the layer covers the entire first side of the wafer.

8. The method of

claim 2

wherein the dry etch comprises an atmospheric pressure plasma etch.

9. The method of

claim 2

wherein after the groove is exposed from the second surface, the dry etch continues and smoothens the groove'"'"'s sidewall.

10. The method of

claim 2

wherein the semiconductor wafer comprises circuitry made at the first side of the wafer, the second side is a backside opposite to the first side, and the groove is formed along a scribe line on the first side.

11. The method of

claim 2

wherein the groove is formed with a diamond saw or a laser.

12. The method of

claim 2

wherein the dry etch rounds one or more of the edges and corners which are obtained on the second side of the wafer when the one or more openings are exposed.

13. The method of

claim 12

wherein the dry etch rounds all of the edges and corners on the second side of each semiconductor chip obtained from the wafer in the dry etch.

14. The method of

claim 2

wherein from a start of the thinning operation until the groove is exposed, the dry etch etches the second side of the wafer uniformly.

15. The method of

claim 2

wherein the entire dry etch is an unmasked etch of the second surface.

16. A semiconductor chip obtained by the method of

claim 1

.

17. A semiconductor chip obtained by the method of

claim 2

.

18. A semiconductor chip obtained by the method of

claim 12

.

19. A semiconductor chip obtained by the method of

claim 13

.

20. A semiconductor ship having a first surface that has a rounded edge or a rounded corner.

21. The semiconductor chip of

claim 20

in which all of the edges and corners of the first surface are rounded.

22. The semiconductor chip of

claim 20

wherein the first surface is a back surface of the chip, the chip having circuitry formed at its front surface which is opposite to the back surface.