Chip device and method for producing the same

• US 20010001293A1
• Filed: 01/05/2001
• Published: 05/17/2001
• Est. Priority Date: 02/27/1998
• Status: Active Grant

• Current Assignee: TDK Corporation
• Original Assignee: TDK Corporation
• Inventors: Kuwajima, Hajime, Gotoh, Masashi, Kanazawa, Jitsuo
• Granted Patent: US 6,417,026 B2
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H03H 9/059 consisting of mounting pads or bumps
• CPC Class Codes: H03H 9/1085 the enclosure being defined by a non-uniform sealing mass covering the non-active sides of the BAW device
• CPC Class Codes: H03H 9/1092 the enclosure being defined by a cover cap mounted on an element forming part of the surface acoustic wave [SAW] device on the side of the IDT's

Abstract

In a chip device in which not only an electrode pattern 25 is provided on a main mounting surface 21a of a base 21 but also bump electrodes 22 are provided as external electrodes for face-down mounting, an electrically insulating layer 31 is provided to be put on at least a part of the main mounting surface 21a so as to remain edge portions which do not cover at least a part of the electrode pattern 25, and a protection layer 32 for protecting the main mounting surface is further provided at a distance from the main mounting surface 21a so as to be put on the electrically insulating layer 31, so that the bump electrodes 22 are connected to the electrode pattern 25 while being in contact with the edge portions of the electrically insulating layer 31 and the protection layer 32.

Claims

1. A chip device comprising:

a base substrate;

an electrode pattern provided on a main mounting surface of said base substrate;

an external electrode provided for face-down mounting; and

an electrically insulating layer formed on at least a part of said main mounting surface in that edge portions are formed to expose at least a part of said electrode pattern;

wherein said external electrodes are connected to said electrode pattern while said external electrodes are in contact with said edge portions of said electrically insulating layer.

2. A chip device according to

claim 1

, wherein said electrically insulating layer includes:

a first electrically insulating layer forming a frame body; and

a second electrically insulating layer provided at a distance from said main mounting surface so as to be put on said first electrically insulating layer to protect said main mounting surface.

3. A chip device according to

claim 1

, wherein saidmain mounting surface has an active region in which comb electrodes for a surface acoustic wave device are formed as a part of said electrode pattern, and said electrically insulating layer is interposed between said main mounting surface and a mount-side substrate while avoiding said active region and comes into close contact with said mount-side substrate to thereby form a closed space which encloses said active region.

4. A chip device according to

claim 2

, wherein said main mounting surface has an active region in which comb electrodes for a surface acoustic wave device are formed as a part of said electrode pattern, and said electrically insulating layer is interposed between said main mounting surface and a mount-side substrate while avoiding said active region and comes into close contact with said mount-side substrate to thereby form a closed space which encloses said active region.

5. A method for producing a chip device comprising the steps of:

forming an electrode pattern on a main mounting surface;

forming at least one electrically insulating layer with a predetermined thickness on at least a part of said main mounting surface so as to remain edge portions which expose at least a part of said electrode pattern;

forming external electrodes so that one end of each of said external electrodes is connected to said electrode pattern while said external electrodes are in contact with said edge portions of said electrically insulating layer.

6. A method for producing a chip device according to

claim 5

, wherein said method further comprises a face-down mounting step of bonding said external electrodes to a mount-side substrate to thereby perform face-down mounting after the external electrode formation step, so that not only said external electrodes are connected to a conductor pattern of said mount-side substrate but also said electrically insulating layer is brought into close contact with both said main mounting surface and the surface of said mount-side substrate in said face-down mounting step.