Nonvolatile semiconductor memory device

• US 20010002172A1
• Filed: 01/23/2001
• Published: 05/31/2001
• Est. Priority Date: 05/14/1997
• Status: Active Grant

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Fumitaka Arai, Hiroshi Nakamura, Ken Takeuchi, Riichiro Shirota, Susumu Fujimura, Tomoharu Tanaka
• Inventors: Fujimura, Susumu, Arai, Fumitaka, Takeuchi, Ken, Tanaka, Tomoharu, Nakamura, Hiroshi, Shirota, Riichiro
• Granted Patent: US 6,434,055 B2
• Time in Patent Office: Days
• US Class Current: 365/185.22
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/345 Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/3463 Circuits or methods to detect overprogrammed nonvolatile memory cells, usually during program verification
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

A NAND cell unit comprising a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

Claims

1. A nonvolatile semiconductor memory device comprising:

a NAND cell unit comprising a plurality of memory cells connected in series;

an erase circuit for applying an erase voltage to all memory cells of said NAND cell unit, thereby to erase data from all memory cells of said NAND cell unit;

a soft-programming circuit for applying a soft-program voltage to all memory cells of said NAND cell unit, said soft-program voltage being of a polarity opposite to the polarity of the erase voltage; and

a programming circuit for applying a program voltage to any selected one of the memory cells, applying a first voltage to at least one of two memory cells adjacent to said any selected one of the memory cells, and applying a second voltage to the remaining memory cells of said NAND cell unit, thereby to program data into said any selected one of the memory cells.

2. A memory device according to

claim 1

, in which said programming circuit for applying the first voltage to both of said two memory cells adjacent to said any selected one of the memory cells.

3. A memory device according to

claim 1

, in which said soft-programming circuit applies the soft-program voltage to all the memory cells after said erasing circuit has erased data from all memory cells of said NAND cell unit, and said programming circuit programs the memory cells after said soft-programming circuit has applied the soft-program voltage to all the memory cells.

4. A memory device according to

claim 1

, in which said soft-program voltage is lower than said program voltage.

5. A memory device according to

claim 1

, which further comprises an erase-verification circuit for determining whether data has been erased from all the memory cells of said NAND cell unit and have threshold voltages controlled within a predetermined range after said soft-programming circuit has applied the soft-program voltage to all the memory cells, and in which said programming circuit programs data into said any selected one of the memory cells after said soft-programming circuit and said erase-verification circuit have performed soft-program operation and erase verification operation.

6. A memory device according to

claim 5

, further comprising a control circuit for causing said soft-programming circuit and said erase-verification circuit to repeat soft-program operation and erase verification operation, and for causing said soft-programming circuit to terminate soft-program operation when at least one of the memory cells of said NAND cell unit has a threshold voltage forced out of the predetermined range.

7. A memory device according to

claim 6

, in which said control circuit causes said erasing circuit to erase data again from all memory cells of said NAND cell unit when the soft-program operation and the erase verification operation have not repeated a predetermined number of times and when at least one of the memory cells of said NAND cell unit is forced out of the predetermined range.

8. A memory device according to

claim 1

, in which the program voltage is higher than the first and second voltages, and the second voltage is higher than the first voltage.

9. A memory device according to

claim 8

, in which the first voltage is 0V.

10. A nonvolatile semiconductor memory device comprising:

a plurality of nonvolatile semiconductor memory cells, each capable of storing n-value data, where n is a natural number greater than 2; and

a data-programming circuit for performing a program operation in which program pulses are applied to said plurality of nonvolatile semiconductor memory cells to program n-value data into said plurality of nonvolatile semiconductor memory cells, performing a program verification operation in which it is determined whether or not the n-value data has been programmed into said plurality of nonvolatile semiconductor memory cells and repeating the program operation and the program verification operation, wherein each of said program pulses has a predetermined pulse width in accordance with a value of the n-value data to be programmed into corresponding memory cell.

11. A memory device according to

claim 10

, in which each program pulse is removed from corresponding memory cell after the program verification operation in which it has been determined that n-value data has been programmed into said corresponding memory cell.

12. A memory device according to

claim 10

, in which the program operation is terminated when it is determined in the program verification operation that all of n-value data have been programmed into said plurality of nonvolatile semiconductor memory cells.

13. A memory device according to

claim 10

, in which the program operation and the program verification operation are terminated after a limited number of cycles.

14. A memory device according to

claim 10

, in which said plurality of nonvolatile semiconductor memory cells are connected to one word line.

15. A memory device according to

claim 10

, in which said plurality of memory cells are respectively included in corresponding NAND cell units, each NAND cell unit comprising a predetermined number of nonvolatile semiconductor memory cells connected in series, and in the program operation, said data-programming circuit applies a first voltage to at least one of the two memory cells adjacent to said selected memory cells to be programmed and a second voltage to the remaining memory cells.

16. A memory device according to

claim 15

, in which voltages of the program pulses are higher than the first and second voltages, and the second voltage is higher than the first voltage.

17. A memory device according to

claim 16

, in which the first voltage is 0V.

18. A nonvolatile semiconductor memory device comprising:

a memory cell array comprising memory cells arranged in rows and columns, each having a control gate;

a programming circuit for programming data into any selected one of said memory cells by applying a program voltage to the control gate of the selected memory cell;

an erasing circuit for erasing data from said memory cells by applying an erase voltage opposite in polarity to the program voltage;

a soft-programming circuit for applying a soft-program to said memory cells, thereby setting the memory cells into a desirable erased state;

a verification read circuit for determining whether said memory cells have been set into the desirable erased state; and

an erased-state determining circuit for causing said soft-programming circuit to terminate the soft-program operation upon determining from an output of said verification read circuit that at least two of said memory cells have a threshold voltage which has reached a predetermined value.

19. A memory device according to

claim 18

, in which said soft-programming circuit soft-programs the memory cells after said erasing circuit has erased data from the memory cells, and said verification read circuit performs a determination operation after said soft-programming circuit has soft-programmed the memory cells.

20. A memory device according to

claim 18

, in which said memory cell array includes a plurality of data input/output lines divided into m units (m>

2), and said erase-state determining circuit comprises circuits for detecting erased states of the memory cells based on the data input/output lines of each unit and causing said soft-programming circuit to terminate soft-program operation, upon determining that at least one of the memory cells connected to the data input/output lines of any unit has a threshold voltage which has reached the predetermined value.

21. A memory device according to

claim 18

, in which said memory cell array includes a plurality of word lines divided into m units (m≧

2), and said erase-state determining circuit comprises circuits for detecting erased states of the memory cells based on the word lines of each unit and causing said soft-programming circuit to terminate soft-program operation, upon determining that at least one of the memory cells connected to the word lines of any unit has a threshold voltage which has reached the predetermined value.

22. A memory device according to

claim 18

, in which the nonvolatile semiconductor memory cells of said memory cell array form NAND cell units, each comprising a plurality of memory cells connected in series, and said programming circuit applies a first voltage lower than the program voltage to the control gate of at least one of two memory cells adjacent to any selected one of the memory cells of each NAND cell unit, and applies a second voltage intermediate between the program voltage and the first voltage, to the remaining memory cells of each NAND cell unit, thereby to program data into said any selected one of the memory cells.

23. A memory device according to

claim 22

, which further comprises a memory circuit for storing data output from the said verification read circuit, and in which said erased-state determining circuit comprises a scan-detection circuit for monitoring the data stored in said memory circuit and counting the memory cells which have a threshold voltage which has reached the predetermined value.

24. A memory device according to

claim 23

, further comprising a control circuit for repeatedly causing said soft-programming circuit to perform a soft-program operation, said verification read circuit to perform a verification read operation and said scan-detection circuit to perform a memory-cell counting operation, and for causing said soft-programming circuit to terminate the soft-program operation, the verification read operation and the memory-cell counting operation when said scan-detection circuit counts at least two memory cells having a threshold voltage which has reached the predetermined value.

25. A memory device according to

claim 24

, in which said control circuit causes said verification read circuit to perform the verification read operation by applying a margin voltage to the word line of each NAND cell unit after said soft-programming circuit has finished performing the soft-program operation, causes said scan-detection circuit to perform the memory-cell counting operation, and causes said soft-programming circuit to terminate the soft-program operation, the verification read operation and the memory-cell counting operation, when said scan-detection circuit detects that all memory cells of each NAND cell unit have a threshold voltage equal to or lower than a predetermined threshold voltage, said predetermined threshold voltage being higher than said predetermined value.

26. A nonvolatile semiconductor memory device comprising:

a memory cell section including at least one memory cell and having first and second ends;

a first signal line connected to the first end of said memory cell section;

a second signal line connected to the second end of said memory cell section;

a reading circuit connected to said first signal line, for reading said memory cell;

an erasing circuit for erasing data stored in said memory cell; and

an over-erase detecting circuit for detecting whether said memory cell is over-erased,

wherein said over-erase detecting circuit applies a first reference potential to said second signal line, thereby outputting a first read potential to said first signal line, and said reading circuit detects the first read potential.

27. A memory device according to

claim 26

, further comprising a soft-programming circuit for performing soft-program operation on said memory cell when said over-erase detecting circuit detects that said memory cell has been over-erased.

30. A memory device according to

claim 26

, in which said reading circuit includes a first switch for connecting said first signal line to a first node, a sense amplifier for detecting a potential of said first node, and a capacitor connected at one end to said first node and at the other end to said second node, and the potential applied to said second node is changed when said sense amplifier detects the potential of said first node.

31. A memory device according to

claim 26

, in which said reading circuit includes a first switch for connecting said first signal line to a first node, a sense amplifier for detecting a potential of said first node, and a capacitor connected at one end to said first node and at the other end to said second node, the potential applied to said second node is changed when said sense amplifier detects the potential of said first node, said over-erase detecting circuit applies the first reference potential to said second signal line to detect whether said memory cell has been over-erased, the first read potential output to said first signal line is transferred through said first switch to said first node as a second read potential, and the potential of said first node is changed to a third read potential different from the second read potential, by changing potential of said second node.

36. A memory device according to

claim 26

, in which said first reference potential is a power-supply voltage.

37. A memory device according to

claim 26

, in which said memory cell section includes a NAND cell unit comprising a plurality of memory cells connected in series.

38. A memory device according to

claim 26

, in which when said over-erase detecting circuit applies the first reference potential to said second signal line, a first over-erase detection word-line potential is applied to the gate of any selected memory cell and a second over-erase detection word-line potential is applied to the gates of the memory cells connected in series to said any selected memory cell, thereby the first read potential is output to said first signal line.

39. A memory device according to

claim 38

, in which the first and second over-erase detection word-line potentials are of approximately the same value.

40. A memory device according to

claim 38

, in which the first and second over-erase detection word-line potentials are of different values.

41. A memory device according to

claim 38

, in which said first over-erase detection word-line potential is 0V.

42. A memory device according to

claim 38

, in which said second over-erase detection word-line potential is a power-supply voltage.

28. A nonvolatile semiconductor memory device comprising:

a first memory cell section including at least one memory cell;

a second memory cell section including at least one memory cell;

a first signal line connected to a first end of said first memory cell section;

a second signal line connected to a second end of said first memory cell section;

a third signal line connected to a first end of said second memory cell section;

a fourth signal line connected to a second end of said second memory cell section;

a reading circuit connected to said first signal line, for reading said memory cell;

an erasing circuit for erasing data stored in said memory cell; and

an over-erase detecting circuit for detecting whether said memory cell is over-erased, wherein said over-erase detecting circuit applies a first reference potential to said second signal line, thereby outputting a first read potential to said first signal line and applying a second reference potential to said third signal line, and said reading circuit detects the first read potential.

29. A nonvolatile semiconductor memory device comprising:

a first memory cell section including at least one memory cell;

a second memory cell section including at least one memory cell;

a first signal line connected to a first end of said first memory cell section;

a second signal line connected to a second end of said first memory cell section;

a third signal line connected to a first end of said second memory cell section;

a fourth signal line connected to a second end of said second memory cell section;

a reading circuit connected to said first signal line, for reading said memory cell;

an erasing circuit for erasing data stored in said memory cell;

an over-erase detecting circuit for detecting whether said memory cell is over-erased; and

a soft-programming circuit for performing soft-program operation on said memory cell when said over-erase detecting circuit detects that said memory cell has been over-erased, wherein said over-erase detecting circuit applies a first reference potential to said second signal line, thereby outputting a first read potential to said first signal line and applying a second reference potential to said third signal line, and said reading circuit detects the first read potential.

32. A memory device according to

claim 29

, in which said first and third lines are bit lines.

33. A memory device according to

claim 29

, in which said first line is a bit line, and said third line is a bit line adjacent to the first line.

34. A memory device according to

claim 29

, in which said second and fourth lines are source lines.

35. A memory device according to

claim 29

, in which said first and second reference potentials are of approximately the same value.

43. A nonvolatile semiconductor memory device comprising:

a memory cell section including a NAND cell unit comprising a plurality of memory cells connected in series;

an erasing circuit for erasing data stored in said memory cells; and

an over-erase detecting circuit for detecting whether said memory cells are over-erased.

44. A memory device according to

claim 43

, further comprising a soft-programming circuit for performing soft-program operation on any one of said memory cells that has been over-erased.

45. A memory device according to

claim 43

, which further comprises a first signal line connected to one end of said NAND cell unit, a second signal line connected to the other end of said NAND cell unit, and a reading circuit connected to said first signal line, for reading said memory cells, and in which said reading circuit includes a first switch for connecting said first signal line to a first node, a sense amplifier for detecting a potential of said first node and a capacitor connected at one end to said first node and a the other end to said second node, and said second node is changed, when said sense amplifier detects the potential of said first node.

46. A memory device according to

claim 45

, further comprising a transistor which includes a gate connected to an output terminal of said sense amplifier and which detects that said second sense amplifier stores the data that one of said memory cells has been erased.

47. A memory device comprising:

a first signal line connected to one end of a unit of memory cells;

a second signal line connected to the other end of the unit of memory cells; and

a reading circuit connected to said first signal line, for reading said memory cells, and wherein

said reading circuit includes a first switch for connecting said first signal line to a first node, a sense amplifier for detecting a potential of said first node and a capacitor connected at one end to said first node and a the other end to said second node, and said second node is changed, when said sense amplifier detects the potential of said first node.

48. A memory device according to

claim 47

, in which a potential of said second signal line is set to a potential higher than a potential of said first signal line during a reading operation.