Fuse for use in a semiconductor device, and semiconductor devices including the fuse

• US 20010002322A1
• Filed: 01/12/2001
• Published: 05/31/2001
• Est. Priority Date: 04/16/1999
• Status: Active Grant

• Current Assignee: Kenneth W. Marr, Michael P. Violette
• Original Assignee: Kenneth W. Marr, Michael P. Violette
• Inventors: Violette, Michael P., Marr, Kenneth W.
• Granted Patent: US 6,410,367 B2
• Time in Patent Office: Days
• US Class Current: 438/132
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A metal silicide fuse for a semiconductor device. The fuse includes a conductive region positioned adjacent a common well of a first conductivity type, a terminal region positioned adjacent a well of a second conductivity type, and a narrowed region located between the terminal region and the conductive region and positioned adjacent a boundary between the two wells. Upon applying at least a programming current to the fuse, the fuse “blows” at the narrowed region. The diode or diodes between wells of different conductivity types wells and the Schottky diode or diodes between the remaining portions of the fuse and wells adjacent thereto control the flow of current through the remainder of the fuse and through the associated wells of the semiconductor device. When the fuse has been “blown”, the diodes and Schottky diodes prevent current of a normal operating voltage from flowing through the wells of the semiconductor device.

Claims

1. A method for fabricating a fuse of a semiconductor device, comprising:

doping a first region of a semiconductor substrate to have a first conductivity type;

doping at least two spaced apart second regions of said semiconductor substrate adjacent said first region to have a second conductivity type;

disposing a layer comprising metal silicide adjacent said semiconductor substrate, including said first region and said at least two spaced apart second regions; and

patterning said layer to define at least two terminal regions of the fuse, each of said at least two terminal regions disposed adjacent a corresponding one of said at least two spaced apart second regions, a conductive region of the fuse disposed between said at least two terminal regions, and a narrowed region of the fuse disposed between said conductive region and one of said at least two terminal regions and positioned adjacent a boundary between one of said at least two spaced apart second regions and said first region.

2. The method of

claim 1

, wherein said doping said first region comprises doping said first region to have a n-type conductivity.

3. The method of

claim 1

, wherein said doping said at least two spaced apart second regions comprises doping said at least two spaced apart second regions to have a p-type conductivity.

4. The method of

claim 1

, wherein said disposing said layer comprising metal silicide comprises chemical vapor depositing said layer.

5. The method of

claim 1

, wherein said disposing said layer comprising metal silicide comprises disposing a layer comprising metal adjacent at least said semiconductor substrate and annealing said metal to silicon or polysilicon adjacent said layer.

6. The method of

claim 5

, further comprising disposing a layer comprising silicon or polysilicon adjacent said layer comprising metal.

7. The method of

claim 6

, further comprising annealing said metal to at least said silicon or polysilicon of the adjacent layer.

8. The method of

claim 1

, wherein said patterning comprises disposing a mask over said layer comprising metal silicide and removing selected regions of said layer comprising metal silicide through said mask.

9. The method of

claim 8

, wherein said disposing said mask comprises:

disposing photoresist on the semiconductor device;

exposing selected regions of said photoresist; and

developing said selected regions.

10. The method of

claim 8

, wherein said removing comprises etching said selected regions of said layer comprising metal silicide.

11. The method of

claim 5

, wherein said patterning comprises disposing a mask over said layer comprising metal and removing selected regions of said layer through said mask.

12. The method of

claim 11

, wherein said disposing said mask comprises:

disposing photoresist on the semiconductor device;

exposing selected regions of said photoresist; and

developing said selected regions.

13. The method of

claim 11

, wherein said removing comprises etching said selected regions.

14. The method of

claim 1

, further comprising disposing a contact in communication with each of said at least two terminals.

15. A method for fabricating a semiconductor device structure, comprising:

providing a semiconductor substrate including at least a first well of a first conductivity type adjacent a surface thereof and a second well of a second conductivity type adjacent said first well and said surface;

disposing a layer comprising metal silicide adjacent said surface; and

patterning said layer to include a first region adjacent said first surface, a narrowed region adjacent a boundary between said first well and said second well, and a second region adjacent said second well.

16. The method of

claim 15

, wherein said disposing said layer comprises chemical vapor depositing metal silicide onto said semiconductor substrate.

17. The method of

claim 15

, wherein said disposing said layer comprises disposing a layer comprising metal over said semiconductor substrate and annealing said metal to adjacent silicon or polysilicon.

18. The method of

claim 17

, wherein said disposing said layer comprising metal comprises physical vapor depositing or chemical vapor depositing said metal.

19. The method of

claim 17

, further comprising disposing a layer comprising silicon or polysilicon adjacent said layer comprising metal.

20. The method of

claim 19

, wherein said disposing said layer comprising silicon or polysilicon comprises chemical vapor depositing said silicon or polysilicon.

21. The method of

claim 19

, wherein said disposing said layer comprising silicon comprises disposing said layer comprising silicon or polysilicon between said semiconductor substrate and said layer comprising metal.

22. The method of

claim 19

, wherein said disposing said layer comprising silicon or polysilicon comprises disposing said layer comprising silicon or polysilicon on said layer comprising metal.

23. The method of

claim 19

, wherein said annealing comprises annealing metal of said layer to adjacent silicon or polysilicon of said layer comprising silicon or polysilicon.

24. The method of

claim 17

, wherein said annealing comprises increasing a temperature of at least said layer comprising metal.

25. The method of

claim 17

, wherein said annealing comprises annealing metal of said layer to adjacent silicon or polysilicon of said semiconductor substrate.

26. The method of

claim 15

, wherein said patterning comprises disposing a mask over said layer comprising metal silicide and removing selected regions of said layer comprising metal silicide through said mask.

27. The method of

claim 26

, wherein said disposing said mask comprises:

disposing photoresist adjacent said layer of metal silicide;

exposing selected regions of said photoresist; and

developing said selected regions.

28. The method of

claim 26

, wherein said removing comprises etching said selected regions.

29. The method of

claim 17

, wherein said patterning comprises disposing a mask over said layer comprising metal and removing selected regions of said layer through said mask.

30. The method of

claim 29

, wherein said disposing said mask comprises:

disposing photoresist on the semiconductor device structure.

31. The method of

claim 29

, wherein said removing comprises etching said selected regions.

32. The method of

claim 15

, further comprising disposing a contact in communication with said first region.

33. The method of

claim 32

, further comprising disposing a second contact in communication with said first well.