Etching mask, process for forming contact holes using same, and semiconductor device made by the process

• US 20010002731A1
• Filed: 11/30/2000
• Published: 06/07/2001
• Est. Priority Date: 12/01/1999
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Ueda, Yasuhiko
• Granted Patent: US 6,559,486 B2
• Time in Patent Office: Days
• US Class Current: 257/750
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers

Abstract

An etching mask having high etching selectivity for an inorganic inter layer film of SiO₂ or Si₃N₄, an organic interlayer film such as ARC and an electrically conductive film and a contact hole using such an etching mask, a process for forming same and a resultant semiconductor device. On formation of contact holes for connecting wirings disposed through interlayer films of inorganic or organic material (20, 23 in FIG. 2), a thin film of silicon carbide (21 in FIG. 2) having high etching selectivity for any of the inorganic and organic materials is deposited on an interlayer film, and a mask pattern of silicon carbide is formed using a resist pattern (22 in FIG. 2). Thereafter, high aspect ratio contact holes having a size which is exactly same as that of the mask is formed by etching the interlayer film using the silicon carbide mask.

Claims

1. An etching mask for forming contact holes to connect wiring layers which sandwich an interlayer film therebetween, wherein said etching mask comprises silicon carbide.

2. An etching mask as defined in

claim 1

, wherein said etching mask is an insulating film having a volume resistivity of 1E14 Ω

cm or more.

3. A process for forming contact holes to connect wiring layers which sandwich an interlayer film therebetween comprising the steps of:

(a) forming a thin film of silicon carbide on an inter layer film through which said contact holes will be formed;

(b) forming a resist pattern on said silicon carbide film;

(c) dry-etching exposed portions of said silicon carbide film using said resist pattern as a mask;

(d) removing said resist pattern by dry or wet-etching; and

(e) forming contact holes through said interlayer film using said silicon carbide film as a mask.

4. The process for forming contact holes as defined in

claim 3

, wherein said interlayer film comprises a stacked layer structure including an inorganic insulating film and organic insulating film.

5. The process for forming contact holes as defined in

claim 4

, wherein said interlayer film comprises a layer made of an electrically conductive film.

6. The process for forming contact holes as defined in

claim 4

, wherein said inorganic insulating film comprises any one of silicon oxide film or silicon nitride film, and wherein said organic insulating film comprises any one selected from the group consisting of benzocyclobutene, polyimide, SiLK (trade name) and FLARE (trade name).

7. The process for forming contact holes as defined in

claim 5

, wherein said inorganic insulating film comprises any one of silicon oxide film or silicon nitride film, and wherein said organic insulating film comprises any one selected from the group consisting of benzocyclobutene, polyimide, SiLK (trade name) and FLARE (trade name).

8. A semiconductor device comprising:

wiring layers and at least one interlayer film,

said wiring layers being disposed on and under the inter layer film, and connected to one another through contact holes which are formed to extend through said interlayer film, wherein an insulating film of silicon carbide is disposed between said inter layer film and said wiring layer disposed on said interlayer film.

13. The semiconductor device as defined in

claim 8

, wherein said contact holes have been formed using said silicon carbide film as an etching mask.

9. A semiconductor device comprising:

a semiconductor substrate;

at least one a gate electrode and source/drain regions on said substrate; and

a plurality of interlayer films and a plurality of wiring layers which are stacked on said gate electrode,

said gate electrode(s) and said wiring layers being connected to one another through contact holes formed to extend through at least one interlayer film, wherein at least one of said contact holes extends through said interlayer films comprising inorganic and organic interlayer films.

11. The semiconductor device as defined in

Claim 9

, wherein said contact holes are formed using an etching mask made of silicon carbide.

10. A semiconductor device comprising:

a semiconductor substrate;

at least one gate electrode and source/drain regions thereon; and

a plurality of interlayer films and a plurality of wiring layers which are stacked on said gate electrode,

said gate electrode(s) and said wiring layers being connected to one another through contact holes formed to extend through said interlayer films,

wherein at least one of said contact holes is formed to extend through a silicon nitride film which is disposed to cover said gate electrode(s) and one of said interlayer films which is deposited on said gate electrode.

12. The semiconductor device as defined in

claim 10

, wherein said contact holes are formed using an etching mask made of silicon carbide.