Secured master-slave D type flip-flop circuit

• US 20010004220A1
• Filed: 12/19/2000
• Published: 06/21/2001
• Est. Priority Date: 12/21/1999
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Pomet, Alain
• Granted Patent: US 6,424,196 B2
• Time in Patent Office: Days
• US Class Current: 327/203
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: H03K 3/0372 of the master-slave type
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors

Abstract

A master-slave D type flip-flop circuit includes a power consumption circuit including a reference stage in parallel with a master and a slave stage of the flip-flop circuit. This structure advantageously provides a switching of the flip-flop circuit on each of the leading and trailing edges of the clock signal for the sequencing of the flip-flop circuit.

Claims

1. A master-slave D type flip-flop circuit comprising a master stage followed by a slave stage, the two stages having an identical structure comprising a first pass gate for the transmission, on an internal node, of an input data element, a storage loop with inverters, connected to said internal node to supply a data element at output of the stage and comprising a second pass gate for the transmission, on said internal node, of the data element complementary to the output data element, wherein the flip-flop circuit furthermore comprises a power consumption masking circuit comprising in parallel, at each of the stages, namely the master and slave stage, a reference stage with a similar structure whose storage loop is disconnected from the output of the associated master or slave stage, the second pass gate of the storage loop of the reference stage being connected between the output of the associated master stage or slave stage and the internal node of the reference stage.

2. A master-slave D type flip-flop circuit according to

claim 1

, wherein the storage loop in each of the reference stages is formed by a load that is equivalent, when seen from the internal node of the stage, to the chain of inverters of the storage loop of the master stage or slave stage.

3. An integrated circuit comprising several master-slave D type flip-flops according to

claim 1

or

2

.

4. An integrated circuit according to

claim 3

, wherein said flip-flop circuits form registers to process confidential data.

5. A smart card or microcircuit comprising an integrated circuit according to

claim 3

or

4

.

6. An electronic system using a smart card or a microcircuit according to

claim 5

.