Circuit and system for extracting data
First Claim
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1. A data extracting circuit comprising:
- a clock transfer section, including multiple unit delay devices connected in series together, for propagating an input clock signal through the delay devices;
an edge detecting section for locating an edge of the clock signal, which edge is being propagated through the clock transfer section, for a time represented by a given edge of an input data signal, and for outputting an edge detection signal indicating the clock signal edge located;
a clock selecting section for selecting one of outputs of the delay devices responsive to the edge detection signal; and
a latch for receiving the output, selected by the selecting section, and the data signal as clock and data inputs, respectively, and for outputting read data.
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Abstract
A data extracting circuit extracts data much more accurately at a much higher response speed. A clock transfer section propagates an input clock signal through unit delay devices thereof. An edge detecting section locates an edge of the clock signal, which edge is being propagated through the clock transfer section, for a time represented by a given edge of an input data signal. In response to an edge detection signal indicating the clock signal edge located, a clock selecting section selects one of outputs of the delay devices, and presents the output as a clock input to a latch.
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18 Claims
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1. A data extracting circuit comprising:
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a clock transfer section, including multiple unit delay devices connected in series together, for propagating an input clock signal through the delay devices;
an edge detecting section for locating an edge of the clock signal, which edge is being propagated through the clock transfer section, for a time represented by a given edge of an input data signal, and for outputting an edge detection signal indicating the clock signal edge located;
a clock selecting section for selecting one of outputs of the delay devices responsive to the edge detection signal; and
a latch for receiving the output, selected by the selecting section, and the data signal as clock and data inputs, respectively, and for outputting read data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 15, 16)
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8. A data extracting circuit comprising:
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a clock transfer section, including multiple unit delay devices connected in series together, for propagating an input clock signal through the delay devices;
an edge detecting section for locating an edge of the clock signal, which edge is being propagated through the clock transfer section, for a time represented by a given edge of an input data signal, and for outputting an edge detection signal indicating the clock signal edge located;
a first group of switches provided for the respective delay devices, each said switch of the first group selectively delivering the output of associated one of the delay devices responsive to the edge detection signal;
a selected clock transfer section including multiple unit transfer gates that are connected in series together and that receive the outputs of the respective switches of the first group;
a first data transfer section, including multiple unit transfer gates connected in series together, for propagating the input data signal through the transfer gates thereof;
a second group of switches provided for the respective transfer gates of the first data transfer section, each said switch of the second group selecting the output of associated one of the transfer gates responsive to the edge detection signal;
a second data transfer section, including multiple unit transfer gates that are connected in series together and that receive the outputs of the respective switches of the second group; and
a Iatch for receiving an output of the second data transfer section and an output of the selected clock transfer section as data and clock inputs, respectively, and for outputting read data. - View Dependent Claims (9, 10, 11, 12, 13, 14, 17, 18)
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Specification