Multilayer ceramic capacitor

• US 20010006449A1
• Filed: 12/12/2000
• Published: 07/05/2001
• Est. Priority Date: 12/24/1999
• Status: Active Grant

• Current Assignee: Taiyo Yuden Company Limited (Taiyo Yuden Co)
• Original Assignee: Taiyo Yuden Company Limited (Taiyo Yuden Co)
• Inventors: Chazono, Hirokazu
• Granted Patent: US 6,362,947 B1
• Time in Patent Office: Days
• US Class Current: 361/306.3
• CPC Class Codes: H01G 4/30 Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: Y10T 29/435 Solid dielectric type

Abstract

A multilayer ceramic capacitor includes a substantially cuboid-shaped laminated body formed with alternately stacked conductive layers and ceramic dielectric layers, and a pair of external electrodes respectively disposed at opposite end portions of the laminated body. The conductive layers are corrugated, and each of the conductive layers has a nonuniform and spatially varying thickness. Thus the surface area of the conductive layers is substantially increased, which in turn results in the increment of the electrostatic capacitance of the multilayer ceramic capacitor. Further, interrupted regions having the layer thickness of zero are formed on the conductive layer and since the boundary portions are pointed toward neighboring conductive layers, a strong electric field is formed thereat. Accordingly, the electrostatic capacitance becomes increased.

Claims

1. A multilayer ceramic capacitor, comprising:

a laminated body formed by alternately stacked ceramic dielectric layers and conductive layers,

wherein the ceramic dielectric layers and the conductive layers are corrugated and the conductive layers have a nonuniform thickness.

2. The multilayer ceramic capacitor of

claim 1

, wherein the conductive layers are provided with interrupted regions devoid of a conductive material.

3. The multilayer ceramic capacitor of

claim 2

, wherein boundary portions of the conductive layers, close to the interrupted regions, are curved upward or downward toward a stacking direction of the ceramic dielectric layers and the conductive layers.

4. The multilayer ceramic capacitor of

claim 3

, wherein a boundary portion points toward one of its neighboring conductive layers.

5. The multilayer ceramic capacitor of

claim 1

, wherein corrugations of the ceramic dielectric layers and the conductive layers run substantially parallel to each other.

6. The multilayer ceramic capacitor of

claim 1

, a conductive paste used in forming the conductive layers includes a conductive material and a ceramic material with a ratio of 100 to about 30-50 in weight.

7. The multilayer ceramic capacitor of

claim 6

, wherein the ceramic material is commonly used in forming the ceramic dielectric layers.

8. The multilayer ceramic capacitor of

claim 1

, wherein the conductive layers are formed by sintering layers of the conductive paste having a thickness of less than about 3 μ

m.

9. The multilayer ceramic capacitor of

claim 8

, wherein the layers of the conductive paste have a thickness of less than about 1 μ

m.

10. A method for forming the multilayer ceramic capacitor of

claim 1

.

11. The method of

claim 10

, comprising the steps of:

stacking ceramic green sheets having a conductive paste coated thereon; and

pressing the stacked ceramic green sheets with a die having grooves on a pressing surface thereof, wherein an average depth of the grooves is between about 10 and 30% of an average thickness of a ceramic green sheet.