Read circuit of nonvolatile semiconductor memory
First Claim
1. A read circuit of a nonvolatile semiconductor memory comprising:
- at least one sense amplifier; and
a read control signal generating circuit for supplying a first signal to said at least one sense amplifier, wherein said at least one sense amplifier has a first current path comprised of a first P-channel MOS transistor having a source electrically connected to a first power supply node and a gate applied with said first signal, and a first N-channel MOS transistor connected between a drain of said first P-channel MOS transistor and a memory cell and having a gate applied with a second signal, and said read control signal generating circuit has a second current path comprised of a second P-channel MOS transistor having a gate and a drain connected to the gate of said first P-channel MOS transistor and a source electrically connected to said first power supply node, and a second N-channel MOS transistor connected between the drain of said second P-channel MOS transistor and a reference cell and having a gate applied with a third signal.
1 Assignment
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Accused Products
Abstract
An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.
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Citations
46 Claims
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1. A read circuit of a nonvolatile semiconductor memory comprising:
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at least one sense amplifier; and
a read control signal generating circuit for supplying a first signal to said at least one sense amplifier, wherein said at least one sense amplifier has a first current path comprised of a first P-channel MOS transistor having a source electrically connected to a first power supply node and a gate applied with said first signal, and a first N-channel MOS transistor connected between a drain of said first P-channel MOS transistor and a memory cell and having a gate applied with a second signal, and said read control signal generating circuit has a second current path comprised of a second P-channel MOS transistor having a gate and a drain connected to the gate of said first P-channel MOS transistor and a source electrically connected to said first power supply node, and a second N-channel MOS transistor connected between the drain of said second P-channel MOS transistor and a reference cell and having a gate applied with a third signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 22, 23, 31, 32, 35, 38, 39, 40)
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8. A read circuit of a nonvolatile semiconductor memory comprising:
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at least one sense amplifier; and
a read control signal generating circuit for supplying a first signal to said at least one sense amplifier, wherein said at least one sense amplifier has a first current path comprised of a first P-channel MOS transistor having a source electrically connected to a first power supply node and a gate applied with said first signal, and a first N-channel MOS transistor connected between a drain of said first P-channel MOS transistor and a memory cell and having a gate applied with a second signal, and said read control signal generating circuit has a second current path comprised of a second P-channel MOS transistor having a gate and a drain connected to the gate of said first P-channel MOS transistor and a source electrically connected to said first power supply node, and a second N-channel MOS transistor connected between the drain of said second P-channel MOS transistor and a reference cell and having a gate applied with said second signal. - View Dependent Claims (9, 10, 11, 12, 13, 14, 24, 25, 33, 34, 36, 41, 42, 43)
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15. A read circuit of a nonvolatile semiconductor memory comprising:
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at least one sense amplifier; and
a read control signal generating circuit for supplying a first signal to said at least one sense amplifier, wherein said at least one sense amplifier includes;
a first inverter comprised of a first P-channel MOS transistor having a source electrically connected to a first power supply node;
a first N-channel MOS transistor connected between a drain of said first P-channel MOS transistor and a memory cell, and having a gate applied with a second signal;
a second P-channel MOS transistor having a gate applied with said first signal, a source electrically connected to said first power supply node, and a drain connected to the gate of said first N-channel MOS transistor; and
a second N-channel MOS transistor having a gate connected to a first connection node between said first N-channel MOS transistor and said memory cell, a source connected to a second power supply node, and a drain connected to the gate of said first N-channel MOS transistor; and
a third N-channel MOS transistor having a gate connected to the gate of said first N-channel MOS transistor, a drain connected to said first power supply node through a switch transistor, and a source connected to said first connection node, and a bit line is precharged in a read operation by supplying charges from said third N-channel MOS transistor to said first connection node. - View Dependent Claims (16, 17, 18, 19, 21, 26, 27, 28, 29, 30, 37, 44, 45, 46)
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20. A constant current source comprising:
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a differential amplifier;
first and second P-channel MOS transistors equal in size to each other, each of said first and second P-channel MOS transistor having a gate applied with an output signal of said differential amplifier and a source connected to a first power supply node; and
a resistor element connected between a drain of said first P-channel MOS transistor and a second power supply node, wherein said differential amplifier is applied with a reference potential at a first input terminal thereof, said differential amplifier has a second input terminal connected to the drain of said first P-channel MOS transistor, and a constant current is output from a drain of said second P-channel MOS transistor.
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Specification