SHARED EMBEDDED MICROCONTROLLER INTERFACE

• US 20010007117A1
• Filed: 03/14/1997
• Published: 07/05/2001
• Est. Priority Date: 03/14/1997
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: COOPER, BARNES, KARDACH, JAMES
• Granted Patent: US 6,446,153 B2
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

A computer system is described where one or more processors executing operating system (OS) code and System Management (SM) code can access the same host interface of an embedded controller. The embedded controller, in turn, is coupled to one or more system devices such as an IDE power plane switch, a thermal A/D monitor, a System Management Bus (SMBus), etc. The embedded controller asserts a system management interrupt (SMI) to the system management environment of the processing unit(s) as well as a system control interrupt to the operating system environment of the processing unit(s). Accordingly, the processing unit(s) executing operating system code and system management code is able to control and/or monitor a number of system devices in the computer system by communicating with the embedded controller via its host interface and interrupts.

Claims

1. A computer system comprising:

a central processing unit adapted to execute operating system code stored in a first memory area and to execute system management code stored in a second memory area;

an embedded controller including a host interface coupled to said central processing unit;

a first interrupt output coupled to said central processing unit, said first interrupt being used by said central processing unit during the execution of said operating system code; and

a second interrupt output coupled to said central processing unit, said second interrupt being used by said central processing unit during the execution of said system management code; and

said embedded controller coupled to at least one system device in said computer system, said central processing unit communicating with said embedded controller via said host interface and said first and second interrupts while executing said operating system code and said system management code such that said central processing unit is capable of at least one of monitoring and controlling said system device via said embedded controller.

2. The computer system of

claim 1

wherein said central processing unit is executing operating system code and communicates with said embedded controller by writing command information to a command register of said embedded controller;

receiving the first interrupt from said embedded controller at said processing unit and exchanging data between said embedded controller and said processing unit while executing operating system code.

3. The computer system of

claim 1

wherein said central processing unit is executing system management code and communicates with said embedded controller by writing command information to a command register of said embedded controller;

receiving the second interrupt from said embedded controller at said processing unit and exchanging data between said embedded controller and said processing unit while executing system management code.

4. The computer system of

claim 1

, further comprising:

an additional embedded controller including a host interface coupled to said central processing unit;

a first interrupt output coupled to said central processing unit, said first interrupt being used by said central processing unit during the execution of said operating system code; and

a second interrupt output coupled to said central processing unit, said second interrupt being used by said central processing unit during the execution of said system management code; and

said additional embedded controller coupled to at least one additional system device in said computer system, said central processing unit communicating with said embedded controller via said host interface and said first and second interrupts while executing said operating system code and said system management code such that said central processing unit is capable of at least one of monitoring and controlling said additional system device via said additional embedded controller.

5. A computer system comprising:

a first processing unit adapted to execute operating system code stored in a first memory area;

a second processing unit adapted to execute system management code stored in a second memory area;

an embedded controller including

a host interface coupled to each of said first and second processing units;

a first interrupt output coupled to at least said first processing unit, said first interrupt being used by said first processing unit during the execution of said operating system code; and

a second interrupt output coupled to at least said second processing unit, said second interrupt being used by said second processing unit during the execution of said system management code; and

said embedded controller coupled to at least one system device in said computer system, said first and second processing units communicating with said embedded controller via said host interface and said first and second interrupts while executing said operating system code and said system management code, respectively such that said each of said processing units is capable of at least one of monitoring and controlling said system device via said embedded controller.

6. The computer system of

claim 5

wherein said first processing unit is executing operating system code and communicates with said embedded controller by writing command information to a command register of said embedded controller;

receiving the first interrupt from said embedded controller at said first processing unit and exchanging data between said embedded controller and said first processing unit executing operating system code.

7. The computer system of

claim 5

wherein said second processing unit is executing system management code and communicates with said embedded controller by writing command information to a command register of said embedded controller;

receiving the second interrupt from said embedded controller at said first processing unit and communicating with said embedded controller by said second processing unit executing system management code.

8. The computer system of

claim 5

, further comprising:

an additional embedded controller including

a host interface coupled to each of said first and second processing units;

a first interrupt output coupled to at least said first processing unit, said first interrupt being used by said first processing unit during the execution of said operating system code; and

a second interrupt output coupled to at least said second processing unit, said second interrupt being used by said second processing unit during the execution of said system management code; and

said additional embedded controller coupled to at least one additional system device in said computer system, said first and second processing units communicating with said additional embedded controller via said host interface and said first and second interrupts while executing said operating system code and said system management code, respectively such that said each of said processing units is capable of at least one of monitoring and controlling said additional system device via said embedded controller.

9. A method of operating a computer system including a central processing unit and a embedded controller coupled to said central processing unit via a host interface and at least one system device coupled to said embedded controller, comprising:

executing operating system code stored in a first memory area by a central processing unit;

executing system management code stored in a second memory area by said central processing unit;

outputting a first interrupt from said embedded controller to said central processing unit, said first interrupt being used by said central processing unit during execution of said operating system code;

outputting a second interrupt from said embedded controller to said central processing unit, said second interrupt being used by said central processing unit during execution of said system management code; and

communicating between said central processing unit and said embedded controller via said host interface and said first and second interrupts while executing said operating system code and said system management code such that said central processing unit is capable of at least one of monitoring and controlling said system device via said embedded controller.

10. The method of

claim 9

wherein said communicating step further includes:

writing command information to a command register of said embedded controller by said processing unit;

receiving the first interrupt from said embedded controller at said processing unit; and

exchanging data between said embedded controller and said processing unit executing operating system code.

11. The method of

claim 9

further comprising:

determining whether said command register contains command information;

placing notification information of said system device in an output buffer of said host interface by said embedded controller if said command register does not contain command information;

receiving the first interrupt from said embedded controller at said processing unit; and

transferring said notification information from said embedded controller to said processing unit executing operating system code.

12. The method of

claim 9

wherein said communicating step further includes:

writing command information to a command register of said embedded controller by said processing unit;

receiving the second interrupt from said embedded controller at said processing unit; and

exchanging data between said embedded controller and said processing unit executing system management code.

13. The method of

claim 9

further comprising:

determining whether said command register contains command information;

placing notification information of said system device in an output buffer of said host interface by said embedded controller if said command register does not contain command information;

receiving the second interrupt from said embedded controller at said processing unit; and

transferring said notification data from said embedded controller to said processing unit executing system management code.

14. A method of operating a computer system including at least first and second processing units and a embedded controller coupled to said processing units via a host interface and at least one system device coupled to said embedded controller, comprising:

executing operating system code stored in a first memory area by a first processing unit;

executing system management code stored in a second memory area by a second processing unit;

outputting a first interrupt from said embedded controller to said first processing unit, said first interrupt being used by said first processing unit during execution of said operating system code;

outputting a second interrupt from said embedded controller to said second processing unit, said second interrupt being used by said central processing unit during execution of said system management code; and

communicating between said processing units and said embedded controller via said host interface and said first and second interrupts while executing said operating system code and said system management code such that said processing units are capable of at least one of monitoring and controlling said system device via said embedded controller.

15. The method of

claim 14

wherein said communicating step further includes:

writing command information to a command register of said embedded controller by said first processing unit;

receiving the first interrupt from said embedded controller at said first processing unit; and

exchanging data between said embedded controller and said first processing unit executing operating system code.

16. The method of

claim 14

further comprising:

determining whether said command register contains command information;

placing notification information of said system device in an output buffer of said host interface by said embedded controller if said command register does not contain command information;

receiving the first interrupt from said embedded controller at said first processing unit; and

transferring said notification information from said embedded controller to said first processing unit executing operating system code.

17. The method of

claim 14

wherein said communicating step further includes:

writing command information to a command register of said embedded controller by said second processing unit;

receiving the second interrupt from said embedded controller at said second processing unit; and

exchanging data between said embedded controller and said second processing unit executing system management code.

18. The method of

claim 14

further comprising:

determining whether said command register contains command information;

placing notification information of said system device in an output buffer of said host interface by said embedded controller if said command register does not contain command information;

receiving the second interrupt from said embedded controller at said second processing unit; and

transferring said notification data from said embedded controller to said second processing unit executing system management code.