Micromachined chip scale package

• US 20010007372A1
• Filed: 01/25/2001
• Published: 07/12/2001
• Est. Priority Date: 03/07/1996
• Status: Active Grant

• Current Assignee: David R. Hembree, Salman Akram, Warren M. Farnworth
• Original Assignee: David R. Hembree, Salman Akram, Warren M. Farnworth
• Inventors: Farnworth, Warren M., Hembree, David R., Akram, Salman
• Granted Patent: US 6,407,451 B2
• Time in Patent Office: Days
• US Class Current: 257/724
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1319 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/13339 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array, or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.

Claims

1. A multi-semiconductor die assembly, comprising:

at least one first chip scale semiconductor die package, comprising;

at least one first semiconductor die made of a semiconductor material and including an integrated circuit having external electrical connections on an active side thereof; and

a discrete preformed blank made of the same semiconductor material as the at least one first semiconductor die is made and having a bondable surface having surface dimensions not in excess of surface dimensions of the active side of the at least one first semiconductor die and including apertures preformed therein through which the external electrical connections of the at least one first semiconductor die are accessible, placed over the active side of the at least one first semiconductor die and secured thereto by the bondable surface with a bonding material to form a laminate comprising the at least one first semiconductor die, and the discrete preformed blank bonded together; and

at least one second chip scale semiconductor die package comprising at least one second semiconductor die made of a semiconductor material and including an integrated circuit having external electrical connections on an active side thereof, the at least one second chip scale semiconductor die package positioned adjacently opposite the at least one first chip scale semiconductor die package in an active side-to-active side facing relationship and at least one external electrical connection of the at least one first semiconductor die in electrical communication with at least one electrical connection of the at least one second semiconductor die.

2. The multi-semiconductor die assembly of

claim 1

, wherein the external electrical connections of at least one of the at least one first semiconductor die and the at least one second semiconductor die comprise bond pads.

3. The multi-semiconductor die assembly of

claim 1

, wherein the external electrical connections of the at least one first semiconductor die comprise bond pads and the external electrical connections of the at least one second semiconductor die comprise bond pads.

4. The multi-semiconductor die assembly of

claim 1

, wherein at least one of the at least one first chip scale semiconductor die and the at least one second chip scale semiconductor die comprises a plurality of dies.

5. The multi-semiconductor die assembly of

claim 1

, wherein the same semiconductor material of the at least one first chip scale semiconductor die package comprises silicon.

6. The multi-semiconductor die assembly of

claim 1

, wherein the same semiconductor material of the at least one first chip scale semiconductor die package comprises GaAs.

7. The multi-semiconductor die of

claim 1

, wherein at least one of the at least one first chip scale semiconductor die and the at least one second chip scale semiconductor die comprises a passivation layer on at least a portion of the active surface thereof.

8. The multi-semiconductor die of

claim 1

, wherein the passivation layer on at least a portion of the active surface comprises at least one of an oxide and a nitride.

9. The multi-semiconductor die assembly of

claim 1

, wherein at least a portion of the exterior of the laminate of the at least one first chip scale semiconductor die package is passivated.

10. The multi-semiconductor die assembly of

claim 1

, wherein the electrical connections of the at least one first semiconductor die comprise bond pads and the apertures of the discrete preformed blank of the at least one first chip scale semiconductor die package are in alignment with the bond pads of the at least one first semiconductor die.

11. The multi-semiconductor die assembly of

claim 1

, further comprising a passivation layer disposed on the active side of at least one of the at least one first semiconductor die and the at least one second semiconductor die.

12. The multi-semiconductor die assembly of

claim 1

, wherein the at least one electrical connection of the at least one first semiconductor die in electrical communication with the at least one electrical connection of the at least one second semiconductor die comprises at least one of electrically conductive solder, electrically conductive epoxy, and electrically conductive polymer.

13. The multi-semiconductor die assembly of

claim 12

, wherein the at least one electrical connection of the at least one first semiconductor die in electrical communication with the at least one electrical connection of the at least one second semiconductor die comprises at least one of an electrically conductive ball, an electrically conductive bump, an electrically conductive pillar, and an electrolessly-plated conductive bump.

14. The multi-semiconductor die assembly of

claim 1

, wherein the at least one second chip scale semiconductor die package comprises:

a discrete preformed blank made of the same semiconductor material as the at least one second semiconductor die is made and having a bondable surface having surface dimensions not in excess of surface dimensions of the active side of the at least one second semiconductor die and including apertures preformed therein through which the external electrical connections of the at least one second semiconductor die are accessible, placed over the active side of the at least one second semiconductor die and secured thereto by the bondable surface with a bonding material to form a laminate comprising the at least one second semiconductor die, and the discrete preformed blank bonded together.

15. The multi-semiconductor die assembly of

claim 14

, wherein the external electrical connections of at least one of the at least one first semiconductor die and the at least one second semiconductor die comprise bond pads.

16. The multi-semiconductor die assembly of

claim 14

, wherein the external electrical connections of the at least one first semiconductor die comprise bond pads and the external electrical connections of the at least one second semiconductor die comprises bond pads.

17. The multi-semiconductor die assembly of

claim 14

, wherein at least one of the at least one first semiconductor die and the at least one second semiconductor die comprises a plurality of dies.

18. The multi-semiconductor die assembly of

claim 14

, wherein the same semiconductor material of the at least one second chip scale semiconductor die package comprises silicon.

19. The multi-semiconductor die assembly of

claim 14

, wherein the same semiconductor material of the at least one second chip scale semiconductor die package comprises GaAs.

20. The multi-semiconductor die of

claim 14

, wherein at least one of the at least one first chip scale semiconductor die and the at least one second chip scale semiconductor die comprises a passivation layer on at least a portion of the active surface thereof.

21. The multi-semiconductor die of

claim 14

, wherein the passivation layer on at least a portion of the active surface comprises at least one of an oxide and a nitride.

22. The multi-semiconductor die assembly of

claim 14

, wherein at least a portion of the exterior of the laminate of the at least one second chip scale semiconductor die package is passivated.

23. The multi-semiconductor die assembly of

claim 14

, wherein the external electrical connections of the at least one second semiconductor die comprise bond pads and the apertures of the discrete preformed blank of the second chip scale semiconductor die package are in alignment with the bond pads of the at least one second semiconductor die.

24. The multi-semiconductor die assembly of

claim 14

, wherein at least some of the apertures in the discrete preformed blank of the second chip scale semiconductor die package are positioned at locations remote from the external electrical connections of the at least one second semiconductor die.

25. The multi-semiconductor die assembly of

claim 14

, further comprising a passivation layer disposed on the active side of at least one of the at least one first second semiconductor die and the at least one second semiconductor die.

26. The multi-semiconductor die assembly of

claim 14

, wherein the at least one electrical connection of the at least one first semiconductor die in electrical communication with the at least one electrical connection of the at least one second semiconductor die comprises at least one of electrically conductive solder, electrically conductive epoxy, and electrically conductive polymer.

27. The multi-semiconductor die assembly of

claim 25

, wherein the at least one electrical connection of the at least one first semiconductor die in electrical communication with the at least one electrical connection of the at least one second semiconductor die comprises at least one of an electrically conductive ball, an electrically conductive bump, an electrically conductive pillar, and an electrolessly-plated conductive bump.

28. The multi-semiconductor die assembly of

claim 14

, wherein the at least one first chip scale semiconductor package comprises a plurality of first chip scale semiconductor packages and the at least one second chip scale semiconductor package comprises a plurality of second chip scale semiconductor packages.

29. The multi-semiconductor die assembly of

claim 28

, wherein at least one of the group consisting of the plurality of first chip scale semiconductor die packages and the plurality of second chip scale semiconductor die packages comprise unsevered semiconductor dies of at least a portion of a semiconductor wafer.

30. The multi-semiconductor die assembly of

claim 28

, wherein the plurality of first chip scale semiconductor die packages are unsevered from a first semiconductor wafer.

31. The multi-semiconductor die assembly of

claim 28

, wherein the plurality of second chip scale semiconductor die packages are unsevered from a second semiconductor wafer.

32. The multi-semiconductor die assembly of

claim 31

, wherein at least a portion of the first semiconductor wafer is passivated and at least a portion of the second semiconductor wafer is passivated.

42. The multi-semiconductor die assembly of

claim 32

, further comprising a passivation layer disposed on at least a portion of the active side of at least one of the at least one first semiconductor die and the at least one second semiconductor die.

33. A multi-semiconductor die assembly, comprising:

at least one first chip scale semiconductor die package, comprising;

at least one first semiconductor die made of a semiconductor material and including an integrated circuit having external electrical connections on an active side thereof; and

a discrete preformed blank having a bondable surface having surface dimensions not in excess of surface dimensions of the active side of the at least one first semiconductor die and including apertures preformed therein through which the external electrical connections of the at least one first semiconductor die are accessible, placed over the active side of the at least one first semiconductor die and secured thereto by the bondable surface with a bonding material to form a laminate comprising the at least one first semiconductor die, and the discrete preformed blank bonded together, wherein at least some of the apertures are positioned in the discrete preformed blank at locations remote from the external electrical connections of the at least one first semiconductor die; and

at least one second chip scale semiconductor die package comprising at least one second semiconductor chip made of a semiconductor material and including an integrated circuit having external electrical connections on an active side thereof, the at least one second chip scale semiconductor die package positioned adjacently opposite the at least one first chip scale semiconductor die package in an active side-to-active side facing relationship and at least one external electrical connection of the at least one first semiconductor die in electrical communication with at least one electrical connection of the at least one second semiconductor die.

34. The multi-semiconductor die assembly of

claim 33

, wherein the external electrical connections of at least one of the at least one first semiconductor die and the at least one second semiconductor die comprise bond pads.

35. The multi-semiconductor die assembly of

claim 33

, wherein at least one of the at least one first chip scale semiconductor die and the at least one second chip scale semiconductor die comprises a plurality of dies.

36. The multi-semiconductor die assembly of

claim 33

, wherein the semiconductor material of at least one of the at least one first chip scale semiconductor die comprises at least one of silicon and GaAs.

37. The multi-semiconductor die assembly of

claim 33

, wherein the discrete preformed blank of the at least one first chip scale semiconductor die package comprises at least one of silicon and GaAs.

38. The multi-semiconductor die assembly of

claim 33

, wherein the discrete preformed blank of the at least one first chip scale semiconductor die package is made of the same semiconductor material as the at least one first semiconductor die.

39. The multi-semiconductor die assembly of

claim 38

, wherein the same semiconductor material of the at least one first chip scale semiconductor die package comprises at least one of silicon and GaAs.

40. The multi-semiconductor die assembly of

claim 33

, wherein at least a portion of at least one of the exterior of the laminate of the at least one first chip scale semiconductor die package is passivated.

41. The multi-semiconductor die assembly of

claim 33

, wherein the apertures of the discrete preformed blank of the at least one first chip scale semiconductor die package are in alignment with the electrical connections of the at least one second semiconductor die.

43. The multi-semiconductor die assembly of

claim 33

, wherein the at least one electrical connection of the at least one first semiconductor die in electrical communication with the at least one electrical connection of the at least one second semiconductor die comprises at least one of electrically conductive solder, electrically conductive epoxy, and electrically conductive polymer.

44. The multi-semiconductor die assembly of

claim 43

, wherein the at least one electrical connection of the at least one first semiconductor die in electrical communication with the at least one electrical connection of the at least one second semiconductor die comprises at least one of an electrically conductive ball, an electrically conductive bump, an electrically conductive pillar, and an electrolessly-plated conductive bump.

45. The multi-semiconductor die assembly of

claim 33

, further comprising circuit traces extending from the external electrical connections of the at least one first semiconductor die to the remote aperture locations of the discrete preformed blank of the at least one first chip scale semiconductor die package.

46. The multi-semiconductor die assembly of

claim 45

, wherein the circuit traces are at least partially disposed on the active surface of the at least one first semiconductor die.

47. The multi-semiconductor die assembly of

claim 45

, wherein the circuit traces are at least partially disposed on the discrete preformed blank of the at least one first chip scale semiconductor die package.

48. The multi-semiconductor die assembly of

claim 33

, wherein the at least one second chip scale semiconductor die package comprises:

a discrete preformed blank made having a bondable surface having surface dimensions not in excess of surface dimensions of the active side of the at least one second semiconductor die and including apertures preformed therein through which the external electrical connections of the at least one second semiconductor die are accessible, placed over the active side of the at least one second semiconductor die and secured thereto by the bondable surface with a bonding material to form a laminate comprising the at least one second semiconductor die, and the discrete preformed blank bonded together.

49. The multi-semiconductor die assembly of

claim 48

, wherein the external electrical connections of at least one of the at least one first semiconductor die and the at least one second semiconductor die comprise bond pads.

50. The multi-semiconductor die assembly of

claim 48

, wherein at least one of the at least one first semiconductor die and the at least one second semiconductor die comprises a plurality of dies.

51. The multi-semiconductor die assembly of

claim 48

, wherein the semiconductor material of at least one of the at least one second chip scale semiconductor die comprises at least one of the group consisting of silicon, GaAs, ceramic material, and mullite.

52. The multi-semiconductor die assembly of

claim 48

, wherein the discrete preformed blank of the at least one second chip scale semiconductor die package comprises at least one of the group consisting of silicon, GaAs, ceramic material, and mullite.

53. The multi-semiconductor die assembly of

claim 48

, wherein the discrete preformed blank of the at least one second chip scale semiconductor die package is made of the same semiconductor material as the at least one second semiconductor die.

54. The multi-semiconductor die assembly of

claim 53

, wherein the same semiconductor material of the at least one second chip scale semiconductor die package comprises at least one of silicon and GaAs.

55. The multi-semiconductor die assembly of

claim 48

, wherein at least a portion of the exterior of the laminate of the at least one second chip scale semiconductor die package is passivated.

56. The multi-semiconductor die assembly of

claim 48

, wherein at least some of the apertures in the discrete preformed blank of the second chip scale semiconductor die package are positioned at locations in alignment with at least some of the apertures in the discrete preformed blank of the at least one first chip scale semiconductor die package.

57. The multi-semiconductor die assembly of

claim 48

, wherein at least some of the apertures in the discrete preformed blank of the second chip scale semiconductor die package are positioned at locations remote from the external electrical connections of the at least one second semiconductor die.

58. The multi-semiconductor die assembly of

claim 48

, further comprising a passivation layer disposed on the active side of at least one of the at least one first second semiconductor die and the at least one second semiconductor die.

59. The multi-semiconductor die assembly of

claim 48

, wherein the at least one electrical connection of the at least one first semiconductor die in electrical communication with the at least one electrical connection of the at least one second semiconductor die comprises at least one of electrically conductive solder, electrically conductive epoxy, and electrically conductive polymer.

60. The multi-semiconductor die assembly of

claim 59

, wherein the at least one electrical connection of the at least one first semiconductor die in electrical communication with the at least one electrical connection of the at least one second semiconductor die comprises at least one of an electrically conductive ball, an electrically conductive bump, an electrically conductive pillar, and an electrolessly-plated conductive bump.

61. The multi-semiconductor die assembly of

claim 48

, wherein the at least one first chip scale semiconductor package comprises a plurality of first chip scale semiconductor packages and the at least one second chip scale semiconductor package comprises a plurality of second chip scale semiconductor packages.

62. The multi-semiconductor die assembly of

claim 61

, wherein at least one of the group consisting of the plurality of first chip scale semiconductor die packages and the plurality of second chip scale semiconductor die packages comprise unsevered semiconductor dies of at least a portion of a semiconductor wafer.

63. The multi-semiconductor die assembly of

claim 61

, wherein the plurality of first chip scale semiconductor die packages are unsevered from a first semiconductor wafer.

64. The multi-semiconductor die assembly of

claim 61

, wherein the plurality of second chip scale semiconductor die packages are unsevered from a second semiconductor wafer.

65. The multi-semiconductor die assembly of

claim 64

, wherein at least a portion of the first semiconductor wafer is passivated and at least a portion of the second semiconductor wafer is passivated.

66. The multi-semiconductor die assembly of

claim 57

, further comprising circuit traces extending from the external electrical connections of the at least one second semiconductor die to the remote aperture locations of the discrete preformed blank of the at least one second chip scale semiconductor die package.

67. The multi-semiconductor die assembly of

claim 66

, wherein the circuit traces are at least partially disposed on the active surface of the at least one second semiconductor die.

68. The multi-semiconductor die assembly of

claim 66

, wherein the circuit traces are at least partially disposed on the discrete preformed blank of the at least one second chip scale semiconductor die package.