Non-volatile semiconductor memory device and semiconductor disk device

• US 20010007533A1
• Filed: 01/12/2001
• Published: 07/12/2001
• Est. Priority Date: 01/12/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi Device Engineering Co., Ltd. (Hitachi, Ltd.), Hitachi, Ltd.
• Inventors: Kobayashi, Naoki, Kurata, Hideaki, Saeki, Shunichi
• Granted Patent: US 6,445,615 B2
• Time in Patent Office: Days
• US Class Current: 365/185.11
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A non-volatile semiconductor memory device is capable of having its individual banks controlled separately from the outside, and a semiconductor disk device is capable of proceeding immediately to the next writing to a bank of non-volatile semiconductor memory device which has become ready. Each bank has the independent write operation of data from its data register to memory cells, enabling the transfer of data from the outside to the data register of the bank even during the write operation of other bank from the data register to memory cells thereof.

Claims

1. A non-volatile semiconductor memory device comprising a plurality of banks each including a plurality of word lines, a plurality of bit lines which are arranged to intersect the word lines, a memory cell array made up of non-volatile memory cells located at the intersections of the word lines and bit lines, and a data register which temporarily holds data to be written which is put in from the outside, each of said banks operating to select a word line in accordance with an input command and the combination of input address signals and write data which is held in the data register to all or part of memory cells connected to the selected word line, wherein each of said banks has an independent write operation of data from the data register to memory cells, enabling the transfer of data from the outside to the data register of said bank even during the write operation of other bank from the data register to memory cells thereof.

2. A non-volatile semiconductor memory device according to

claim 1

further comprising a bank selection register which can take states more than the number of said banks, thereby producing a signal for pointing one of said banks depending on the state, said bank selection register having its state established by an input signal from the outside.

3. A non-volatile semiconductor memory device according to

claim 2

, wherein the state of said bank selection register can be read out from the outside.

4. A non-volatile semiconductor memory device according to

claim 1

further comprising a plurality of input terminals of bank enable signals, thereby producing a signal for pointing one of said banks in accordance with the combination of the bank enable signals.

5. A non-volatile semiconductor memory device according to any of claims 1 through 4, wherein said data transfer from the outside to a bank takes place for the data register which belongs to the selected bank.

6. A non-volatile semiconductor memory device according to any of claims 1 through 4, wherein said device releases the state of the selected bank in response to a status checking command from the outside.

7. A non-volatile semiconductor memory device according to any of claims 1 through 4, wherein a read, write, erase or status check commands from the outside act only on a selected bank.

8. A semiconductor disk device which incorporates one or more non-volatile semiconductor memory devices and makes access to said non-volatile semiconductor memory devices in response to disk access requests from a host, wherein said non-volatile semiconductor memory devices have a total number (Nb) of banks of two or more, and a controller device which is connected to said non-volatile semiconductor memory devices and adapted to control said non-volatile semiconductor memory devices has a data buffer with a storage capacity which is greater than the total storage capacity (A) of data registers included in said non-volatile semiconductor memory devices and a buffer control table which temporarily stores the correspondence between the data held by said data buffer and the non-volatile semiconductor memory devices to which the data is to be written.

9. A semiconductor disk device according to

claim 8

, wherein said data buffer has a storage capacity of 2A or more.

10. A semiconductor disk device according to

claim 8

or

9

, wherein said data buffer has storage areas of at least Nb in number which can be addressed separately.

11. A semiconductor disk device according to

claim 10

, wherein said buffer control table stores identifiers indicative of banks to which data held by said buffer regions is to be transferred, said device initiating the writing to said non-volatile semiconductor memory devices while transferring data from a buffer area, which is relevant to a bank which has become ready, to said bank.

12. A semiconductor disk device according to

claim 11

, wherein information stored in the areas of said buffer control table includes information which indicates the priority level of the transfer of data held in the areas of said data buffer to said non-volatile semiconductor memory devices.

13. A semiconductor disk device according to

claim 11

, wherein information stored in the areas of said buffer control table indicates as to whether data held in the regions of said data buffer has been transferred to said non-volatile semiconductor memory devices.

14. A semiconductor disk device according to

claim 8

, wherein said buffer control table contains an information for addressing the data buffer area for each bank of each non-volatile semiconductor memory device, said data buffer area storing data to be transferred to the bank, said device initiating the writing to said non-volatile semiconductor memory devices while transferring data from a buffer area, which is relevant to a bank which has become ready, to said bank.

15. A semiconductor disk device according to

claim 14

, wherein information for each bank stored in said buffer control table includes a plurality of information for addressing the data buffer area, said address information indicating the order of data transfer to said banks.

16. A semiconductor disk device according to

claim 14

or

15

, wherein said information for addressing the data buffer area is designed to address areas of at least Nb in number of said data buffer.