Method of producing a thin layer of semiconductor material

• US 20010007789A1
• Filed: 02/06/2001
• Published: 07/12/2001
• Est. Priority Date: 05/15/1996
• Status: Active Grant

• Current Assignee: Bernard Aspar, Michel Bruel, Thierry Poumeyrol
• Original Assignee: Bernard Aspar, Michel Bruel, Thierry Poumeyrol
• Inventors: Aspar, Bernard, Bruel, Michel, Poumeyrol, Thierry
• Granted Patent: US 6,809,009 B2
• Time in Patent Office: Days
• US Class Current: 438/458
• CPC Class Codes: G03F 7/70541 Tagging, i.e. hardware or software tagging of features or components, e.g. using tagging scripts or tagging identifier codes for identification of chips, shots or wafers
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate
• CPC Class Codes: Y10T 428/24612 Composite web or sheet

Abstract

The invention relates to a method of producing a thin layer of semiconductor material including:

a step of implanting ions through a flat face (2) of a semiconductor wafer in order to create a layer of microcavities, the ion dose being within a specific range in order to avoid the formation of blisters on the flat face,

a thermal treatment step in order to achieve coalescence of the microcavities

possibly, a step of creating at least one electronic component (5) in the thin layer (6),

a separation step of separating the thin layer (6) from the rest (7) of the wafer.

Claims

1. A method of producing a thin layer of semiconductor material from a wafer of said material having a flat face, including an ion implantation step consisting of bombarding said flat face with ions chosen from among the ions of rare gases or of hydrogen, at a specific temperature and a specific dose in order to create, in a plane called a reference plane and situated at a depth proximate to the mean depth of penetration of the ions, microcavities, the method also including a subsequent thermal treatment step at a temperature sufficient to achieve separation of the wafer into two parts, across the reference plane, the part situated on the side of the flat face constituting the thin layer, in which

the ion implantation step is carried out with an ion dose between a minimum dose and a maximum dose, the minimum dose being that from which there will be sufficient creation of microcavities to obtain the embrittlement of the wafer along the reference plane, the maximum dose, or critical dose being that above which, during the thermal treatment, there is separation of the wafer,

a separation step of the wafer into two parts, across the reference plane, is provided after or during the thermal treatment step, this separation step comprising the application of mechanical Forces between the two parts of the wafer.

2. A method according to

claim 1

, comprising, between the thermal treatment step and the separation step, a step consisting of producing all or part of at least one electronic component in the part of the wafer before forming the thin layer.

3. A method according to

claim 2

in which, the production of said electronic component, requiring thermal treatment phases, these are carried out at a temperature below that of the thermal treatment.

4. A method according to

claim 1

, in which, just before the separation step, an extra step is provided that consists of said wafer, on the side of the flat face, being brought into close contact with and being rigidly fixed to, a support through which the mechanical forces will be applied.

5. A method according to

claim 4

, in which said support is a flexible support.

6. A method according to

claim 5

, in which said flexible support is a sheet of Kapton®

.

7. A method according to

claim 4

in which said support is a rigid support.

8. A method according to

claim 7

, in which said rigid support is a wafer of oxidised silicon.

9. A method according to

claim 1

, in which said wafer of semiconductor material is made of monocrystalline silicon.

10. A method according to

claim 1

, in which said wafer of semiconductor material is covered on the side of the flat face, with a layer of non-semiconductor material.

11. A method according to

claim 10

, in which the non-semiconductor material is a dielectric material.

12. A method according to any one of the preceding claims, in which the mechanical forces applied at the time of the separation step are tensile forces and/or shear forces and/or bending forces.