MIS transistor and manufacturing method thereof

• US 20010008293A1
• Filed: 01/26/2001
• Published: 07/19/2001
• Est. Priority Date: 12/10/1996
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Shimizu, Satoshi, Oda, Hidekazu
• Granted Patent: US 6,521,519 B2
• Time in Patent Office: Days
• US Class Current: 257/382
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

This invention provides a MIS transistor with less electrical short between a gate and source/drain electrodes. A sidewall spacer 15 has a two-layer structure including a buffer layer 13 which consists of nitrided oxide silicon and a silicon nitrided layer 14 formed on the buffer layer 13. The sidewall spacer 15 serves as a mask to form a silicide film 10.

Claims

1. A MIS transistor comprising:

a silicon substrate;

a gate insulation film formed on said silicon substrate;

a gate electrode formed on said gate insulation film;

a sidewall spacer including a silicon nitride layer, formed on both sides of said gate electrodes on said silicon substrate in contact with said silicon substrate; and

a silicide film formed outside of said sidewall spacer in said silicon substrate, said silicide film including a metal to be diffusion species for silicon in silicide reaction.

2. The MIS transistor of

claim 1

, wherein

said sidewall spacer including:

a buffer layer formed on both sides of said gate electrodes on said silicon substrate in contact with said silicon substrate; and

a silicon nitride layer formed on said buffer layer.

3. The MIS transistor of

claim 2

, wherein

said buffer layer in said sidewall spacer consists of nitrided oxide silicon.

4. The MIS transistor of

claim 1

, wherein

said metal to be diffusion species for silicon consists of cobalt.

5. The MIS transistor of

claim 1

, wherein

said metal to be diffusion species for silicon consists of nickel.

6. The MIS transistor of

claim 1

, wherein

said metal to be diffusion species for silicon consists of alloy including cobalt.

7. The MIS transistor of

claim 1

, wherein

said metal to be diffusion species for silicon consists of alloy including nickel.

8. A manufacturing method of a MIS transistor comprises steps of:

forming a gate insulation film and a gate electrode, both of a MIS transistor, on a silicon substrate;

forming a sidewall spacer including a silicon nitride layer, on both sides of said gate electrodes on said silicon substrate in contact with said silicon substrate; and

forming a silicide film outside of said sidewall spacer in said silicon substrate by using a metal to be diffusion species for silicon in silicide reaction.

9. The manufacturing method of a MIS transistor of

claim 8

,

said step of forming a sidewall spacer including steps of:

forming a buffer layer on both sides of said gate electrodes on said silicon substrate in contact with said silicon substrate; and

forming said silicon nitride layer on said buffer layer.

10. The manufacturing method of a MIS transistor of

claim 9

,

wherein said buffer layer in said sidewall spacer consists of nitrided oxide silicon.

11. The manufacturing method of a MIS transistor of

claim 8

,

said step of forming a silicide film including a step of:

making cobalt silicide of cobalt and silicon with a single rapid thermal annealing.

12. The manufacturing method of a MIS transistor of

claim 8

,

wherein said metal to be diffusion species for silicon consists of cobalt.

13. The manufacturing method of a MIS transistor of

claim 8

,

wherein said metal to be diffusion species for silicon consists of nickel.

14. The manufacturing method of a MIS transistor of

claim 8

,

wherein said metal to be diffusion species for silicon consists of alloy including cobalt.

15. The manufacturing method of a MIS transistor of

claim 8

,

wherein said metal to be diffusion species for silicon consists of alloy including nickel.