Semiconductor memory and method for controlling the same

• US 20010008492A1
• Filed: 01/17/2001
• Published: 07/19/2001
• Est. Priority Date: 01/18/2000
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Higashiho, Mitsuhiro
• Granted Patent: US 6,542,417 B2
• Time in Patent Office: Days
• US Class Current: 365/196
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A semiconductor memory operates in a write mode and a read mode. The memory includes memory cells, pairs of bit lines connected to the memory cells, sense amplifiers having first and second I/O terminals connected to the bit lines, column selection gates connected to the associated sense amplifiers, and a control circuit. The control circuit controls the sense amplifiers and the column selection gate, so that selected column selection gate turns on before the sense amplifiers are activated during the write mode. The write data is applied to the first I/O terminals of the sense amplifiers. The semiconductor memory thus produced according to the present invention has a reduced circuit size.

Claims

1. A semiconductor memory including a plurality of memory cells and having a write mode, the semiconductor memory comprising:

a plurality of pairs of bit lines connected to the memory cells;

a plurality of sense amplifiers, each having a first I/O terminal and a second I/O terminal which are connected to an associated pair of the bit lines;

a plurality of column selection gates, each connected to the first I/O terminal of an associated one of the sense amplifiers;

a data bus connected to the column selection gates; and

a control circuit connected to the sense amplifiers, wherein the control circuit controls the sense amplifiers and the column selection gate, such that selected column selection gate turns on before the sense amplifiers are activated during the write mode.

2. The semiconductor memory according to

claim 1

, wherein the control circuit detects whether the semiconductor memory is in the write mode or the read mode, upon receiving a semiconductor memory activation command.

3. The semiconductor memory according to

claim 2

, wherein the control circuit activates a corresponding one of the sense amplifiers to amplify a potential at a selected pair of the bit lines before the column selection circuits function upon detecting the read mode.

4. The semiconductor memory according to

claim 2

, further comprising:

a plurality of word lines connected to the memory cells;

a row decoder connected to the word lines to selectively activate the word lines; and

a column decoder connected to the column selection circuits to generate a signal for controlling the column selection circuits, wherein the control circuit generates, in accordance with the activation command, a first control signal for controlling activation and deactivation of the row decoder, a second control signal for controlling the column decoder, and a third control signal for controlling the sense amplifiers.

5. The semiconductor memory according to

claim 4

, further comprising:

a plurality of pairs of transfer gates, wherein each pair of the transfer gates is connected between an associated pair of the bit lines and the first and second I/O terminals of an associated one of the sense amplifiers, and wherein the control circuit generates, in accordance with the activation command, a fourth control signal for controlling the transfer gates.

6. The semiconductor memory according to

claim 1

, further comprising:

a plurality of pairs of transfer gates, wherein each pair of the transfer gates is connected between an associated pair of the bit lines and the first and second I/O terminals of an associated one of the sense amplifiers, wherein the control circuit deactivates the transfer gates when the sense amplifiers are activated.

7. The semiconductor memory according to

claim 6

, wherein the control circuit controls the transfer gates so that the transfer gates are deactivated after the data read from a selected one of the memory cells is transferred to an associated one of the sense amplifiers via a corresponding pair of the bit lines during the read mode, and the transfer gates are deactivated before data is transferred from a pair of the bit lines corresponding to a selected one of the sense amplifiers during the write mode.

8. The semiconductor memory according to

claim 6

, further comprising:

a plurality of word lines connected to the memory cells;

a row decoder connected to the word lines to selectively activate the word lines; and

a column decoder connected to the column selection circuits to generate a signal for controlling the column selection circuits, wherein the control circuit detects whether the semiconductor memory is in the write mode or the read mode upon receiving a semiconductor memory activation command, and wherein the control circuit generates, in accordance with the activation command, a first control signal for controlling activation and deactivation of the row decoder, a second control signal for controlling the column decoder, and a third control signal for controlling the sense amplifiers.

9. The semiconductor memory according to

claim 8

, wherein the control circuit generates, in accordance with the activation command, a fourth control signal for controlling the transfer gates.

10. A method for controlling a semiconductor memory including a plurality of memory cells, a plurality of pairs of bit lines connected to the memory cells, a plurality of sense amplifiers, each connected to an associated pair of the bit lines and having a first I/O terminal and a second I/O terminal, a plurality of column selection gates, each connected to the first I/O terminal of an associated one of the sense amplifiers, and a data bus connected to the column selection gates, wherein the semiconductor memory operates in a write mode and a read mode, such that data is written to the memory cells in the write mode, data is read from the memory cells in the read mode, the method comprising:

selectively operating the column selection circuits to apply a potential of the data bus to the first I/O terminal of a selected one of the sense amplifiers during the write mode; and

activating the selected one of the sense amplifiers during the write mode.

11. The method according to

claim 10

, further comprising:

activating the selected one of the sense amplifiers before selectively operating the column selection circuits, when the semiconductor memory shifts from the write mode to the read mode; and

amplifying a potential at a pair of the bit lines associated with data read from a selected one of the memory cells with the selected one of the sense amplifiers, when the semiconductor memory shifts from the write mode to the read mode.

12. The method according to

claim 10

, wherein the semiconductor memory further includes a plurality of pairs of transfer gates, wherein each pair of the transfer gates is connected between an associated pair of the bit lines and the first and second I/O terminals of an associated one of the sense amplifiers, the method further comprising:

deactivating the transfer gates when the sense amplifiers are activated.

13. The method according to

claim 12

, the method further comprising:

transferring data read from a selected one of the memory cells to an associated one of the sense amplifiers via a corresponding pair of the bit lines during the read mode;

deactivating the transfer gates during the read mode after transferring data read from the selected one of the memory cells;

activating the associated one of the sense amplifiers during the read mode after deactivating the transfer gates;

deactivating the transfer gates before data is transferred from a pair of the bit lines corresponding to a selected one of the sense amplifiers during the write mode; and

activating the associated one of the sense amplifiers during the write mode after deactivating the transfer gates.

14. A method for writing a semiconductor memory, the method comprising:

selectively operating column selection circuits to apply a potential of a data bus to a first I/O terminal of a selected one of sense amplifiers;

then

activating the selected one of the sense amplifiers.