Trench DMOS transistor having reduced punch-through

• US 20010008788A1
• Filed: 03/02/2001
• Published: 07/19/2001
• Est. Priority Date: 09/14/1999
• Status: Active Grant

• Current Assignee: Fwu-Iuan Hshieh, Koon Chong So
• Original Assignee: Fwu-Iuan Hshieh, Koon Chong So
• Inventors: So, Koon Chong, Hshieh, Fwu-Iuan
• Granted Patent: US 6,545,315 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method of forming a trench DMOS transistor is provides which reduces punch-through. The method begins by providing a substrate of a first conductivity type. A body region, which has a second conductivity type, is formed on the substrate. A masking layer is formed which defines at least one trench. Next, the trench and an insulating layer that lines the trench are formed. A conductive electrode is then formed in the trench, which overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. The step of forming the trench includes the steps of etching the trench and smoothing the sidewalls of the trench with a sacrificial oxide layer before removal of the masking layer that defines the trench.

Claims

1. A method of forming a trench DMOS transistor cell comprising the steps of:

providing a substrate of a first conductivity type;

forming a body region on the substrate, said body region having a second conductivity type;

forming a masking layer defining at least one trench;

forming the trench defined by the masking layer, said trench extending through the body region and the substrate;

forming an insulating layer that lines the trench;

forming a conductive electrode in the trench overlying the insulating layer;

forming a source region of the first conductivity type in the body region adjacent to the trench; and

wherein the step of forming the trench includes the steps of etching the trench and smoothing sidewalls of the trench with a sacrificial oxide layer before removal of the masking layer that defines the trench.

2. The method of

claim 1

wherein the step of forming the body region includes the steps of implanting and diffusing a dopant into the substrate.

3. The method of

claim 1

wherein the step of forming the trench includes the step of forming a patterned masking layer over the body region.

4. The method of

claim 3

further comprising the step of removing the sacrificial oxide layer and the patterned masking layer subsequent to formation of the trench.

5. The method of

claim 1

wherein the step of forming the insulating layer lining the trench includes the step of depositing an oxide layer in the trench.

6. The method of

claim 1

wherein the step of forming the conductive electrode includes the step of depositing polysilicon in the trench over the insulating layer.

7. The method of

claim 6

wherein the polysilicon includes a dopant material.

8. The method of

claim 6

wherein the step of depositing polysilicon includes the steps of depositing a layer of undoped polysilicon followed by a layer of doped polysilicon.

9. The method of

claim 1

wherein the step of forming the source region includes the steps of depositing a patterned masking layer and implanting and diffusing a dopant into the body region.

10. A method of forming a trench DMOS transistor cell comprising the steps of:

providing a substrate of a first conductivity type;

forming a body region on the substrate, said body region having a second conductivity type;

forming a masking layer defining at least one trench;

forming the trench defined by the masking layer, said trench extending through the body region and the substrate;

forming an insulating layer that lines the trench;

forming a polysilicon conductive electrode in the trench overlying the insulating layer;

forming a source region of the first conductivity type in the body region adjacent to the trench; and

wherein the step of forming the polysilicon conductive electrode includes the steps of depositing a layer of undoped polysilicon followed by a layer of doped polysilicon.

11. The method of

claim 10

wherein the step of forming the body region includes the steps of implanting and diffusing a dopant into the substrate.

12. The method of

claim 10

wherein the step of forming the trench includes the step of forming a patterned masking layer over the body region.

13. The method of

claim 12

further comprising the step of removing the sacrificial oxide layer and the patterned masking layer subsequent to formation of the trench.

14. The method of

claim 10

wherein the step of forming the insulating layer lining the trench includes the step of depositing an oxide layer in the trench.

15. The method of

claim 10

wherein the step of forming the trench includes the steps of etching the trench and smoothing sidewalls of the trench with a sacrificial oxide layer before removal of the masking layer that defines the trench.

16. The method of

claim 10

wherein the step of forming the source region includes the steps of depositing a patterned masking layer and implanting and diffusing a dopant into the body region.

17. A trench DMOS transistor cell, comprising:

a substrate of a first conductivity type;

a body region on the substrate, said body region having a second conductivity type;

at least one trench extending through the body region and the substrate;

an insulating layer that lines the trench;

a conductive electrode in the trench overlying the insulating layer, said conductive electrode including a doped layer and an undoped layer; and

a source region of the first conductivity type in the body region adjacent to the trench.

18. The DMOS transistor cell of

claim 17

wherein said conductive electrode includes a layer of undoped polysilicon and a layer of doped polysilicon.

19. The DMOS transistor cell of

claim 17

further comprising a drain electrode disposed on a surface of the substrate opposing the body region.

20. The DMOS transistor cell of

claim 17

wherein said insulating layer is an oxide layer.