Semiconductor device and method of manufacturing the same

• US 20010009292A1
• Filed: 12/01/2000
• Published: 07/26/2001
• Est. Priority Date: 12/03/1999
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Suguro, Kyoichi, Akasaka, Yasushi, Nishinohara, Kazumi
• Granted Patent: US 6,541,829 B2
• Time in Patent Office: Days
• US Class Current: 257/402
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location

Abstract

A semiconductor device has a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region, and a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region. The second semiconductor region contains first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region. An insulating film and a conductor are formed on the second semiconductor region. Third and fourth semiconductor regions of the second conductivity type are formed at the semiconductor surface in contact with the side faces of the second semiconductor region. This semiconductor device is capable of suppressing net impurity concentration variations as well as threshold voltage variations to be caused by a short channel effect or manufacturing variations.

Claims

1. A semiconductor device comprising:

a first semiconductor region formed in a semiconductor substrate and having a first conductivity type due to first-conductivity-type active impurities contained in the first semiconductor region;

a second semiconductor region formed between the first semiconductor region and the surface of the semiconductor substrate and having a second conductivity type due to second-conductivity-type active impurities contained in the second semiconductor region, the second semiconductor region also containing first-conductivity-type active impurities whose concentration is zero or smaller than a quarter of a concentration of the second-conductivity-type active impurities contained in the second semiconductor region;

an insulating film formed on the surface of the semiconductor substrate over the second semiconductor region;

a conductor formed on the insulating film;

a third semiconductor region of the second conductivity type formed in contact with the second semiconductor region; and

a fourth semiconductor region of the second conductivity type formed in contact with the second semiconductor region.

2. The semiconductor device of

claim 1

, wherein:

the first-conductivity-type active impurities in the first semiconductor region have a concentration profile that decreases toward the surface of the semiconductor substrate and includes a part where a concentration ratio per 3 nm is smaller than 0.9.

3. The semiconductor device of

claim 1

, wherein:

a concentration of the second-conductivity-type active impurities at the bottom of the second semiconductor region is smaller than half a maximum concentration of the first-conductivity-type impurities contained in a depletion layer formed during the operation of the semiconductor device.

4. The semiconductor device of

claim 1

, wherein:

at the bottom of the second semiconductor region, the gradient of a concentration profile of the second-conductivity-type active impurities is smaller than that of the first-conductivity-type active impurities.

5. The semiconductor device of

claim 1

, wherein:

a concentration of the second-conductivity-type active impurities at the bottom of a depletion layer during the operation of the semiconductor device is smaller than a quarter of a maximum concentration of the first-conductivity-type active impurities in the depletion layer.

6. The semiconductor device of

claim 1

, wherein:

a concentration profile of the second-conductivity-type impurities in the second semiconductor region has a peak on the substrate surface side of the bottom of the second semiconductor region.

7. The semiconductor device of

claim 1

, wherein:

a concentration profile of the second-conductivity-type impurities in the second semiconductor region has a peak where a concentration of the first-conductivity-type active impurities is smaller than half the concentration of the second-conductivity-type active impurities.

8. The semiconductor device of

claim 1

, wherein:

at the surface of the semiconductor substrate, a concentration of the first-conductivity-type active impurities is smaller than a quarter of a concentration of the second-conductivity-type active impurities.

9. The semiconductor device of

claim 1

, wherein:

a concentration of the second-conductivity-type active impurities at the surface of the semiconductor substrate is smaller than ten times a concentration of the second-conductivity-type active impurities at the bottom of the second semiconductor region or smaller than ten times a peak concentration of the second-conductivity-type active impurities in the second semiconductor region, and is larger than one tenth of the concentration of the second-conductivity-type active impurities at the bottom of the second semiconductor region.

10. The semiconductor device of

claim 1

, wherein:

the first-conductivity-type active impurities in the first semiconductor region have a concentration profile that sharply decreases toward the surface of the semiconductor substrate and includes a part where a concentration ration per 1 nm is smaller than 0.9.

11. The semiconductor device of

claim 1

, wherein:

the first-conductivity-type impurities are indium atoms.

12. The semiconductor device of

claim 1

, wherein:

the second-conductivity-type impurities are phosphorus atoms.

13. The semiconductor device of

claim 1

, wherein:

the second-conductivity-type impurities are atoms of a material selected from antimony and arsenic.

14. The semiconductor device of

claim 1

, wherein:

the first-conductivity-type impurities are atoms of a material selected from antimony and arsenic.

15. The semiconductor device of

claim 1

, wherein:

the second-conductivity-type impurities are boron atoms.

16. The semiconductor device of

claim 1

, wherein:

the second-conductivity-type impurities are indium atoms.

17. The semiconductor device of

claim 1

, wherein:

the conductor is made of a material selected from metal and metal compound.

18. The semiconductor device of

claim 1

, wherein:

the semiconductor substrate includes the semiconductor device with the first conductivity type being p and another semiconductor device that is identical with the former semiconductor device except that the first conductivity type is n.

19. The semiconductor device of

claim 18

, wherein:

the conductor of the semiconductor device with the first conductivity type being p and the conductor of the semiconductor device with the first conductivity type being made of the same material selected from metal and metal compound.

20. A method of forming a semiconductor device, comprising:

a first step of introducing first-conductivity-type impurities into first and second regions of a semiconductor substrate, the first region being in the vicinity of the surface semiconductor substrate, the second region being behind the first region away from the surface of the semiconductor substrate, a concentration profile of first-conductivity-type active impurities in the second region being at least four times higher than a concentration profile of first-conductivity-type active impurities in the first region;

a second step of introducing second-conductivity-type impurities into the first region so that a concentration of second-conductivity-type active impurities in the first region is higher than a concentration of the first-conductivity-type active impurities in the first region;

a third step of forming an insulating film on the semiconductor substrate;

a fourth step of forming a conductor on the insulating film; and

a fifth step of forming a semiconductor region of the second conductivity type on each side of the conductor in contact with the second region.

21. The method of

claim 20

, wherein:

the fifth step is first carried out;

an opening is formed and is filled with the conductor;

the first step is carried out to introduce the first-conductivity-type impurities into the semiconductor substrate through the opening; and

the third and fourth steps are lastly carried out.

22. The method of

claim 21

, wherein:

the second step is carried out after the formation of the opening.

23. The method of

claim 21

, wherein:

the second step is carried out before the fifth step.

24. The method of

claim 20

, wherein:

the insulating film is formed by chemical vapor deposition.

25. The method of

claim 20

, wherein:

no steps after the fourth step maintain temperatures higher than 850 degrees centigrade for more than 60 seconds.

26. A semiconductor device comprising:

a semiconductor substrate containing first conductive impurities;

a semiconductor layer containing second conductive impurities whose conductivity type is opposite to that of the first conductive impurities, formed on the semiconductor substrate and having a groove whose bottom is the surface of the semiconductor substrate;

an insulator layer covering the bottom and side walls of the groove; and

a conductor layer formed on the insulator layer in the groove,

a surface area of the semiconductor substrate having an impurity diffusion layer that contains second conductive impurities whose concentration is lower than a concentration of the second conductive impurities in the semiconductor layer,

a pattern formed by the semiconductor layer including the groove being identical with a pattern formed by the impurity diffusion layer.

27. The semiconductor device of

claim 26

, wherein:

the impurity diffusion layer has a uniform thickness.

28. The semiconductor device of

claim 26

, wherein:

the second conductive impurities in the impurity diffusion layer are uniformly distributed in a depth direction.

29. The semiconductor device of

claim 26

, wherein:

the impurity diffusion layer, semiconductor layer, insulator layer, and conductor layer form a semiconductor element;

the semiconductor device further has an element isolation film surrounding the semiconductor element; and

the top surface of the element isolation film and the top surface of the semiconductor layer are substantially in the same plane.

30. A method of manufacturing a semiconductor device, comprising the steps of:

forming a semiconductor layer on a semiconductor substrate, the semiconductor substrate containing first conductive impurities, the semiconductor layer containing second conductive impurities whose conductivity type is opposite to that of the first conductive impurities;

forming an impurity diffusion layer by partly diffusing the second conductive impurities contained in the semiconductor layer into a surface area of the semiconductor substrate;

forming, after the formation of the impurity diffusion layer, a groove through the semiconductor layer, the bottom of the groove being the surface of the semiconductor substrate;

forming an insulator layer on the semiconductor layer, to cover the bottom and side walls of the groove and leave a space in the groove; and

forming a conductor layer on the insulator layer to fill at least part of the space in the groove.