Semiconductor device and process for producing the same

• US 20010009295A1
• Filed: 01/17/2001
• Published: 07/26/2001
• Est. Priority Date: 01/18/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Systems Company Limited (Hitachi, Ltd.)
• Inventors: Ryuzaki, Daisuke, Furusawa, Takeshi, Sakuma, Noriyuki, Machida, Shuntaro, Hinode, Kenji, Yoneyama, Ryou
• Granted Patent: US 6,358,838 B2
• Time in Patent Office: Days
• US Class Current: 257/635
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/31633 Deposition of carbon doped silicon oxide, e.g. SiOC
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An intermetal insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a film thickness shrinkage at a time of oxidation of 14% or less is very low in dielectric constant, high in selectivity against resist etching and can be used without using a silicon oxide protective film in a semiconductor device.

Claims

1. A semiconductor device including one or more intermetal insulating films, each intermetal insulating film containing at least silicon atoms, oxygen atoms, and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a shrinkage in the film thickness direction at a time of oxidation of 14% or less.

2. A semiconductor device according to

claim 1

, wherein the shrinkage in the film thickness direction at the time of oxidation is 10% or less.

3. A semiconductor device according to

claim 1

, wherein the intermetal insulating film has a relative dielectric constant of 3.5 or less.

4. A semiconductor device according to

claim 1

, wherein the intermetal insulating film has all of Si—

CH₃ bond, Si—

O—

Si bond and Si—

C—

Si bond.

5. A process for producing a semiconductor device comprising

a step of forming an intermetal insulating film using a mixed gas comprising a vapor of monomethyltriethoxysilane represented by the formula:

RSi(OR′

)₃, wherein R is a methyl group and R′

is an ethyl group, and a non-oxidizing gas by means of a plasma chemical vapor deposition method, and

a step of forming wires.

6. A process according to

claim 5

, wherein the non-oxidizing gas is a nitrogen gas, a hydrogen gas, an ammonia gas, a helium gas, an argon gas or a mixture thereof.

7. A process according to

claim 5

, wherein the non-oxidizing gas is a mixture of a nitrogen gas and an inert gas.

8. A process according to

claim 5

, wherein the intermetal insulating film is formed under a condition of (pressure in a reactor)·

(volume of the reactor)/(total gas flow rate) of 500 Torr.sec or less.

9. A process according to

claim 8

, wherein the intermetal insulating film is formed under a condition of (pressure in a reactor)·

(volume of the reactor)/(total gas flow rate) of 280 Torr.sec or less.

10. A process for producing a semiconductor device which comprises

a step of forming an intermetal insulating film using a mixed gas comprising a vapor of methylethoxysilane represented by the formula:

R_nSi(OR′

)_4-n, wherein R is a methyl group, R′

is an ethyl group, and n is 0 to 2, said vapor being mixed so as to make R 0.75 to 1.5 per silicon, and a non-oxidizing gas by means of a plasma chemical vapor deposition method, and

a step of forming wires.

11. A process according to

claim 10

, wherein the non-oxidizing gas is a nitrogen gas, a hydrogen gas, an ammonia gas, a helium gas, an argon gas or a mixture thereof.

12. A process according to

claim 10

, wherein the non-oxidizing gas is a mixture of a nitrogen gas and an inert gas.

13. A process according to

claim 10

, wherein the intermetal insulating film is formed under a condition of (pressure in a reactor)·

(volume of the reactor)/(total gas flow rate) of 500 Torr.sec or less.

14. A process according to

claim 13

, wherein the intermetal insulating film is formed under a condition of (pressure in a reactor)·

(volume of the reactor)/(total gas flow rate) of 280 Torr.sec or less.

15. A process for producing a semiconductor device which comprises

a step of forming an intermetal insulating film using a mixed gas comprising (a) a vapor of monomethyltriethoxysilane represented by the formula:

RSi(OR′

)₃, wherein R and R′

are each methyl group, or (b) a vapor of methylmethoxysilane represented by the formula;

R_nSi(OR′

)_4-n, wherein R and R′

are each methyl group, and n is 0 to 2, said vapor being mixed so as to make R 0.75 to 1.5 per silicon, and a non-oxidizing gas by means of a plasma chemical vapor deposition method, and

a step of forming wires.

16. A process according to

claim 15

, wherein the non-oxidizing gas is a nitrogen gas, a hydrogen gas, an ammonia gas, a helium gas, an argon gas or a mixture thereof.

17. A process according to

claim 15

, wherein the non-oxidizing gas is a mixture of a nitrogen gas and an inert gas.

18. A process according to

claim 15

, wherein the intermetal insulating film is formed under a condition of (pressure in a reactor)·

(volume of the reactor)/(total gas flow rate) of 500 Torr.sec or less.

19. A process according to

claim 18

, wherein the intermetal insulating film is formed under a condition of (pressure in a reactor)·

(volume of the reactor)/(total gas flow rate) of 280 Torr.sec or less.

20. A process for producing a semiconductor device which comprises

a step forming an intermetal insulating film containing at least silicon atoms, oxygen atoms, and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a shrinkage in the film thickness direction at a time of oxidation of 14% or less,

a step of forming one or more trenches or holes in the intermetal insulating film,

a step of depositing a metal film so as to fill the trenches or holes, and

a step of removing the metal film from portions other than insides of the trenches or holes by chemical-mechanical polishing process.

21. A process according to

claim 20

, which further comprises a step of exposing the intermetal insulting film to plasma containing oxygen under a pressure of 50 mTorr or less.

22. A process for producing a semiconductor device which comprises

a step forming an intermetal insulating film containing at least silicon atoms, oxygen atoms, and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a shrinkage in the film thickness direction at a time of oxidation of 10% or less,

a step of forming one or more trenches or holes in the intermetal insulating film,

a step of depositing a metal film so as to fill the trenches or holes, and

a step of removing the metal film from portions other than insides of the trenches or holes by chemical-mechanical polishing process.

23. A process according to

claim 22

, which further comprises a step of exposing the intermetal insulting film to plasma containing oxygen under a pressure of 50 mTorr or less.

24. A process for producing a semiconductor device which comprises

a step of forming a first wire by dry etching of a metal film,

a step of forming a first insulating film containing at least silicon atoms, oxygen atoms, and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a shrinkage in the film thickness direction at a time of oxidation of 14% or less,

a step of forming a coated insulating film,

a step of forming a second insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a shrinkage in the film thickness direction at a time of oxidation of 14% or less,

a step of forming holes in a stack comprising the first insulating film, the coated insulating film and the second insulating film so as to expose a surface of the first wire,

a step of filling a metal film in the holes, and

a step of removing the metal film from outside of the holes.

25. A process according to

claim 24

, which further comprises a step of removing a resist used for forming the holes by a plasma treatment containing at least oxygen under a pressure of 50 mTorr or less between the step of forming the holes and the step of filling the metal film in the holes.

26. A process for producing a semiconductor device which comprises

a step of forming a first wire by dry etching of a metal film,

a step of forming a first insulating film containing at least silicon atoms, oxygen atoms, and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a shrinkage in the film thickness direction at a time of oxidation of 10% or less,

a step of forming a coated insulating film,

a step of forming a second insulating film containing at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and having a shrinkage in the film thickness direction at a time of oxidation of 10% or less,

a step of forming holes in a stack comprising the first insulating film, the coated insulating film and the second insulating film so as to expose a surface of the first wire,

a step of filling a metal film in the holes, and

a step of removing the metal film from outside of the holes.

27. A process according to

claim 26

, which further comprises a step of removing a resist used for forming the holes by a plasma treatment containing at least oxygen under a pressure of 50 mTorr or less between the step of forming the holes and the step of filling the metal film in the holes.

28. A semiconductor device including one or more wiring layers, each layer having a plurality of inlaid wires and intermetal insulating films between individual inlaid wires, said intermetal insulating film being a single layer film of a low dielectric constant film having a dielectric constant lower than that of a silicon oxide film.

29. A semiconductor device according to

claim 28

, wherein the low dielectric constant film contains at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and has a shrinkage in the film thickness direction at a time of oxidation of 14% or less.

30. A semiconductor device according to

claim 28

, wherein the low dielectric constant film contains at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and has a shrinkage in the film thickness direction at a time of oxidation of 10% or less.

31. A semiconductor device including one or more wiring layers, each layer having a plurality of inlaid wires and intermetal insulating films between individual inlaid wires, said intermetal insulating film being a stack of a plurality of insulating films, the uppermost insulating film being a low dielectric constant film having a dielectric constant lower than that of a silicon oxide film.

32. A semiconductor device according to

claim 31

, wherein the low dielectric constant film contains at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and has a shrinkage in the film thickness direction at a time of oxidation of 14% or less.

33. A semiconductor device according to

claim 31

, wherein the low dielectric constant film contains at least silicon atoms, oxygen atoms and carbon atoms with the number ratio of oxygen atom to silicon atom being 1.5 or more and the number ratio of carbon atom to silicon atom being 1 to 2, and has a shrinkage in the film thickness direction at a time of oxidation of 10% or less.