Semiconductor integrated circuit, computer system, data processor and data processing method

• US 20010010057A1
• Filed: 02/09/2001
• Published: 07/26/2001
• Est. Priority Date: 06/24/1997
• Status: Abandoned Application

• Current Assignee: Intarsia Software LLC (Intellectual Ventures LLC)
• Original Assignee: Matsushita Electric Corporation (Panasonic Holdings Corporation)
• Inventors: Yamada, Toshio
• Application Number:
  US09/779,751
• Publication Number:
  US 20010010057A1
• Time in Patent Office: Days
• US Class Current: 709/203
• CPC Class Codes: G06F 15/7821 Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory

Abstract

A memory having a data processing function is connected with a memory network such as a memory bus. A memory controller writes data to be processed in a predetermined area in the memory having the data processing function. The memory having the data processing function processes the written data and stores resultant processed data. Thereafter, the memory controller reads the stored resultant processed data. Accordingly, work data (intermediate data obtained during the processing) is not transferred to the memory controller through the memory bus but is processed within the memory having the data processing function. As a result, the data processing ability can be improved. In the memory having the data processing function, a processing specification for the processing to be executed is written immediately before executing the processing. Accordingly, no work data is transferred through the memory bus between a CPU and the memory serving as a work area for the processing. Thus, the data processing ability can be improved.

Claims

1. A computer system comprising:

a semiconductor device connected with a memory network and having a data processing function.

14. The computer system, the data processor or the data processing method of

claim 1

,

2

, 3, 4, 5, 10, 12 or 13,

wherein said memory network has a bus network structure.

15. The computer system, the data processor or the data processing method of

claim 1

,

2

, 3, 4, 5, 10, 12 or 13,

wherein said memory network has a ring network structure.

2. A computer system comprising:

a CPU;

a host bus connected with said CPU;

a core logic connected with said CPU through said host bus and including a memory controller;

a memory network connected with said memory controller included in said core logic;

a semiconductor device connected with said memory network and having no data processing function;

a semiconductor device connected with said memory network and having a data processing function;

a peripheral equipment bus connected with said core logic; and

a mass storage device connected with said peripheral equipment bus.

3. The computer system of

claim 2

,

wherein said semiconductor device having the data processing function is formed as a module.

4. A computer system comprising:

a semiconductor device connected with a memory network, serving as a memory accessed by a controller through said memory network and having a data processing function.

5. A computer system comprising:

a semiconductor device connected with a memory network and having a memory emulation function.

6. A data processing method comprising the steps of:

writing data to be processed in a predetermined area within a memory space of a semiconductor device having a data processing function and serving as a memory;

processing said data by said semiconductor device and writing resultant processed data in said predetermined area or another predetermined area within said room; and

obtaining said resultant processed data by reading said predetermined area or said another predetermined area within said room of said semiconductor device after writing said resultant processed data.

7. A data processing method by using a data processor including a controller and a semiconductor device having a data processing function and serving as a memory,

wherein said controller writes specification information of a processing to be executed in a first area within a room of said semiconductor device and writes data to be processed in a second area within said room,

said semiconductor device subsequently processes said data written in said second area on the basis of said processing specification information written in said first area within said room, and writes resultant processed data in a third area within said room, and

said controller reads said resultant processed data from said third area within said room.

8. The data processing method of

claim 7

,

wherein said second area and said third area within said room of said semiconductor device are the same area, and

said semiconductor device overwrites said resultant processed data in said second area where said data has been written.

9. The data processing method of

claim 7

,

wherein said controller reads time information required for said processing to be executed, and reads said resultant processed data written in said third area within said room on the basis of said read time information after time corresponding to said time information elapses.

10. The data processing method of

claim 9

,

wherein said semiconductor device is connected with said controller through a memory network, and

said controller stores time information required for each processing to be executed by said semiconductor device.

11. The data processing method of

claim 7

,

8

, 9 or 10,

wherein, immediately before executing said processing by said semiconductor device having the data processing function, information describing said processing to be executed is dynamically rewritten for executing said processing.

12. A data processor comprising:

a controller;

a semiconductor device connected with said controller through a memory network and having a data processing function; and

informing means for informing said controller that said semiconductor device has the data processing function and what type of data processing function said semiconductor device has.

13. A data processing method by using a data processor including a controller, a semiconductor device connected with said controller through a memory network and having a data processing function and a semiconductor device connected with said memory network and having no data processing function,

wherein said controller repeatedly writes identification request information in a predetermined address of said semiconductor devices connected with said memory network, with a semiconductor device identification address successively varied;

said semiconductor device having the data processing function changes the written identification request information in accordance with the data processing function thereof;

said controller repeatedly reads data stored in said predetermined address of said semiconductor devices connected with said memory network, with said semiconductor device identification address successively varied again; and

said controller recognizes that each of said semiconductor device has or dose not have a data processing function and what type of data processing function said semiconductor device has.

16. A semiconductor integrated circuit comprising:

a semiconductor device serving as a memory and having a data processing function; and

changing means for dynamically changing a relationship between a logical address within a memory address space allocated to said semiconductor device and an actual physical address.

17. A computer system comprising:

plural memory networks; and

a semiconductor device having a data processing function,

wherein said semiconductor device is connected with said plural memory networks and has a data exchange function to transfer data between said plural memory networks.

18. A computer system comprising:

a semiconductor device connected with a memory network and having a data processing function and an image displaying function.