Signal discriminator for wake-up of a low power transponder

• US 20010010491A1
• Filed: 03/05/2001
• Published: 08/02/2001
• Est. Priority Date: 11/02/1999
• Status: Abandoned Application

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Van Niekerk, Johannes Albertus, Marneweck, Willem J.
• Application Number:
  US09/799,287
• Publication Number:
  US 20010010491A1
• Time in Patent Office: Days
• US Class Current: 340/10.33
• CPC Class Codes: B60R 2325/105 Radio frequency identification data [RFID]
• CPC Class Codes: B60R 25/2072 with means for preventing jamming or interference of a remote switch control signal
• CPC Class Codes: B60R 25/24 using electronic identifiers containing a code not memorised by the user
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G07C 2009/00373 whereby the wake-up circuit is situated in the lock
• CPC Class Codes: G07C 2009/0038 whereby the wake-up circuit is situated in the keyless data carrier
• CPC Class Codes: G07C 2009/00587 by battery
• CPC Class Codes: G07C 2009/00793 by Hertzian waves
• CPC Class Codes: G07C 9/00309 operated with bidirectional data transmission between data carrier and locks
• CPC Class Codes: H04W 52/0238 where the received signal is an unwanted signal, e.g. interference or idle signal
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A signal discriminator for preventing activation by undesired signals of low power transponder circuits in a keyless entry system. These undesired signals may be noise or interfering signals. An asymmetrical low pass filter is used to determine the presence of a desired signal having a defined length of time. The asymmetrical filter has a longer charge time then discharge time, thereby being adapted to quickly discharge upon the loss of a signal. Signal duration verification is further used to determine if the desired signal is of a correct time duration.

Claims

1. A keyless entry and security system having a signal discriminator for reducing false wake-up of power consuming circuits, said system comprising:

an interrogator, said interrogator transmits an interrogation signal and listens for a response thereto;

a receiver adapted for reception of the interrogation signal, said receiver having a receiver output and producing a first signal on the receiver output when receiving the interrogation signal; and

an asymmetrical time constant low pass filter having an input connected to the receiver output, wherein a second signal is generated from an output of said asymmetrical time constant low pass filter if the first signal is present for a desired time, and if the first signal is not present for the desired time then the second signal is not generated.

2. The keyless entry and security system of

claim 1

, further comprising a wake-up power control circuit having a power input, power output and a control input, the control input is connected to the output of said asymmetrical time constant low pass filter, wherein power at the power input is connected to the power output when the second signal is received at the control input of said power control circuit.

3. The keyless entry and security system of

claim 2

, further comprising a transponder, said transponder connected to the power output and receiving power therefrom, said transponder having a data input connected to the receiver output for detecting the received interrogation signal and sending a response signal to said interrogator when power is received from the power output of said power control circuit.

4. The keyless entry and security system of

claim 2

, wherein the power input of said wake-up power control circuit is connected to a power source.

5. The keyless entry and security system of

claim 4

, wherein the power source is a battery.

6. The keyless entry and security system of

claim 1

, further comprising a clock inhibit circuit, said clock inhibit circuit being controlled by the second signal such that clock signals are inhibited when there is no second signal present, and the clock signals are enabled when the second signal is present.

7. The keyless entry and security system of

claim 6

, further comprising a transponder, said transponder connected to said clock inhibit circuit, said transponder having a data input connected to the receiver output for detecting the received interrogation signal and sending a response signal to said interrogator when the clock signals are enabled.

8. The keyless entry and security system of

claim 1

, wherein said asymmetrical time constant low pass filter comprises:

a resistor connected between the receiver output and the wake-up input;

a diode connected between the receiver output and the wake-up input; and

a capacitor connected between the wake-up input and a signal common.

9. The keyless entry and security system of

claim 8

, wherein said resistor and said capacitor determine the desired time.

10. The keyless entry and security system of

claim 9

, wherein said resistor is about one megohm and said capacitor is about 2×

10<sup>−

9</sup> farads.

11. The keyless entry and security system of

claim 10

, wherein the desired time is about two milliseconds.

20. The keyless entry and security system of

claim 1

, further comprising signal duration verification logic connected to the output of said asymmetrical time constant low pass filter, wherein the second signal must be less than a certain time before a third signal is generated at an output of said signal duration verification logic.

21. The keyless entry and security system of

claim 20

, further comprising a wake-up power control circuit having a power input, power output and a control input, the control input is connected to the output of said signal duration verification logic, wherein power at the power input is connected to the power output when the third signal is received at the control input of said power control circuit.

22. The keyless entry and security system of

claim 20

, further comprising a clock inhibit circuit, said clock inhibit circuit being controlled by the third signal such that clock signals are inhibited when there is no third signal present, and the clock signals are enabled when the third signal is present.

23. The keyless entry and security system of

claim 20

, wherein said signal duration verification logic comprises:

a signal duration timer;

a no signal timer; and

a signal status memory,

wherein the second signal starts the signal duration timer and resets the no signal timer such that when the second signal is not present and the signal duration timer has not timed out then the signal status memory is set to produce the third signal, if the second signal is present when the signal duration timer times out then the signal status memory does not to produce the third signal, and if there is no second signal when the no signal timer times out then the signal status memory is reset so that no third signal is produced.

12. A method for reducing false wake-up of power consuming circuits in a keyless entry and security system, said method comprising the steps of:

transmitting an interrogation signal and listening for a response signal thereto;

receiving the interrogation signal and producing a first signal therefrom;

delaying the first signal with an asymmetrical time constant low pass filter for a desired time, wherein if the first signal is present for the desired time then generating a second signal;

applying power to a transponder when the second signal is generated; and

transmitting the response signal after power is applied to the transponder to acknowledge the received interrogation signal.

13. The method of

claim 12

, wherein the desired time is determined by a time constant of a resistor and a capacitor.

14. The method of

claim 13

, wherein if the first signal is not present for the desired time the resistor is bypassed with a diode so as to quickly discharge the capacitor.

24. The method of

claim 12

, further comprising the step of verifying that the duration of the second signal is less than a certain time before transmitting the response signal.

25. The method of

claim 24

, wherein the step of verifying that the duration of the second signal is less than a certain time comprises the steps of:

starting a signal duration timer when the second signal is asserted;

resetting a no signal timer when the second signal is asserted; and

generating a third signal when the second signal is not present and the signal duration timer has not timed out, otherwise not generating the third signal; and

resetting the third signal when there is no second signal and the no signal timer has timed out.

15. An apparatus for reducing false wake-up of power consuming circuits in a keyless entry and security system, said apparatus comprising:

a receiver adapted for reception of an interrogation signal, said receiver having a receiver output and producing a first signal on the receiver output when receiving the interrogation signal; and

an asymmetrical time constant low pass filter having an input connected to the receiver output, wherein a second signal is generated from and output of said asymmetrical time constant low pass filter if the first signal is present for a desired time, and if the first signal is not present for the desired time then the second signal is not generated.

16. The apparatus of

claim 15

, further comprising a power control circuit having a power input, power output and a control input connected to the output of said asymmetrical time constant low pass filter, wherein power at the power input is connected to the power output when the second signal is received at the control input of said power control circuit.

17. The apparatus of

claim 16

, further comprising a transponder, said transponder connected to the power output and receiving power therefrom, said transponder having a data input connected to the receiver output for detecting the received interrogation signal and sending a response signal to said interrogator when power is received from the power output of said power control circuit.

18. The apparatus of

claim 16

, wherein the power input of said power control circuit is adapted for connection to a power source.

19. The apparatus of

claim 15

, wherein said asymmetrical time constant low pass filter comprises:

a resistor connected between the receiver output and the wake-up input;

a diode connected between the receiver output and the wake-up input; and

a capacitor connected between the wake-up input and a signal common.

26. The apparatus of

claim 16

, further comprising signal duration verification logic connected to the output of said asymmetrical time constant low pass filter, wherein the second signal must be less than a certain time before a third signal is generated at an output of said signal duration verification logic.

27. The apparatus of

claim 26

, further comprising a wake-up power control circuit having a power input, power output and a control input, the control input is connected to the output of said signal duration verification logic, wherein power at the power input is connected to the power output when the third signal is received at the control input of said power control circuit.

28. The apparatus of

claim 26

, further comprising a clock inhibit circuit, said clock inhibit circuit being controlled by the third signal such that clock signals are inhibited when there is no third signal present, and the clock signals are enabled when the third signal is present.

29. The apparatus of

claim 26

, wherein said signal duration verification logic comprises:

a signal duration timer;

a no signal timer; and

a signal status memory,

wherein the second signal starts the signal duration timer and resets the no signal timer such that when the second signal is not present and the signal duration timer has not timed out then the signal status memory is set to produce the third signal, if the second signal is present when the signal duration timer times out then the signal status memory does not to produce the third signal, and if there is no second signal when the no signal timer times out then the signal status memory is reset so that no third signal is produced.