Semiconductor device and its manufacturing method

• US 20010010941A1
• Filed: 02/28/2001
• Published: 08/02/2001
• Est. Priority Date: 06/26/1998
• Status: Active Grant

• Current Assignee: Etsuo Morita
• Original Assignee: Etsuo Morita
• Inventors: Morita, Etsuo
• Granted Patent: US 7,033,854 B2
• Time in Patent Office: Days
• US Class Current: 438/46
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01S 5/0207 Substrates having a special shape
• CPC Class Codes: H01S 5/0213 Sapphire, quartz or diamond based substrates
• CPC Class Codes: H01S 5/32341 blue laser based on GaN or GaP

Abstract

To improve crystallographic property of a nitride III-V compound semiconductor layer grown on a sapphire substrate, a plurality of recesses are made on a major surface of the sapphire substrate, and the nitride III-V compound semiconductor layer is grown thereon. At least a part of the inner surface of each recess makes an angle not less than 10 degrees with respect to the major surface of the sapphire substrate. The recesses are buried with nitride III-V compound semiconductor crystal having a higher Al composition ratio than the nitride III-V compound semiconductor layer, such as Al_xGa_1−xN crystal whose Al composition ratio x is 0.2 or more, for example. Each recess has a depth not less than 25 nm and a width not less than 30 nm. The recesses may be made either upon thermal cleaning of the sapphire substrate or by using lithography and etching, thermal etching, or the like.

Claims

1. A semiconductor device using a nitride III-V compound semiconductor layer grown on a sapphire substrate, comprising:

recesses made on said sapphire substrate along an interface thereof with said nitride III-V compound semiconductor layer.

2. The semiconductor device according to

claim 1

wherein at least a part of the inner surface of each said recess makes an angle not smaller than 10 degrees with respect to a major surface of said sapphire substrate nearer to said nitride III-V compound semiconductor layer.

3. The semiconductor device according to

claim 1

wherein said one major surface of the sapphire substrate nearer to the nitride III-V compound semiconductor layer includes surfaces inclined by a slight angle from the (0001) plane or the (0001) plane of sapphire crystal.

4. The semiconductor device according to

claim 1

wherein each said recess has a depth not less than 25 nm and a width not less than 30 nm.

5. The semiconductor device according to

claim 1

wherein nitride III-V compound semiconductor crystal having a larger Al composition ratio than said nitride III-V compound semiconductor layer is buried inside said recesses.

6. The semiconductor device according to

claim 5

wherein each said recess has a depth not less than 10 nm and a width not less than 30 nm.

7. The semiconductor device according to

claim 1

wherein nitride III-V compound semiconductor crystal having a larger Al composition ratio than said nitride III-V compound semiconductor layer is provided along the interface between said sapphire substrate and said nitride III-V compound semiconductor layer to plug said recesses.

8. The semiconductor device according to

claim 5

wherein said nitride III-V compound semiconductor layer is made of Al_x1Ga₁₋

x1−

y1In_y1N (0≦

x1≦

1, 0≦

y1≦

1, 0≦

x1+y1<

1) said nitride III-V compound semiconductor crystal is made of Al_x2Ga<sub>1−

x2−

y2</sub>In_y2N (0≦

x2≦

1, 0≦

y2≦

1, 0≦

x2+y2≦

1), and x2−

x1≧

0.1.

9. The semiconductor device according to

claim 7

wherein said nitride III-V compound semiconductor layer is made of Al_x1Ga₁₋

x1−

y1In_y1N (0≦

x1<

1, 0≦

y1≦

1, 0≦

x1+y1≦

1), said nitride III-V compound semiconductor crystal is made of Al_x2Ga<sub>1−

x2−

y2</sub>In_y2N (0≦

x2<

1, 0≦

y2≦

1, 0≦

x2+y2≦

1), and x2−

x1≧

0.1.

10. The semiconductor device according to

claim 5

wherein said nitride III-V compound semiconductor layer is a GaN layer, and said nitride III-V compound semiconductor crystal is made of Al_xGa₁₋

xN where 0.2≦

x≦

1.

11. The semiconductor device according to

claim 7

wherein said nitride III-V compound semiconductor crystal is made of Al_xGa₁₋

xN where 0.2≦

x≦

1.

12. The semiconductor device according to

claim 1

wherein nitride III-V compound semiconductor crystal is plugged inside said recesses, and moire fringes are observed in a transmission electron microscopic image of the portion of said nitride III-V compound semiconductor crystal.

13. The semiconductor device according to

claim 1

wherein nitride III-V compound semiconductor crystal is plugged inside said recesses, and moire fringes with a distance from 1.37 to 1.67 nm are observed in portions of said recesses in a transmission electron microscopic image taken by exciting at least (0002) reflection of said nitride III-V compound semiconductor crystal and (0006) reflection of said sapphire crystal.

14. The semiconductor device according to

claim 10

wherein moire fringes with a distance from 1.37 to 1.67 nm are observed in portions of said recesses in a transmission electron microscopic image taken by exciting at least (0002) reflection of said nitride III-V compound semiconductor crystal and (0006) reflection of sapphire crystal.

15. The semiconductor device according to

claim 11

wherein moire fringes with a distance from 1.37 to 1.67 are observed in portions of said recesses in a transmission electron microscopic image taken by exciting at least (0002) reflection of said nitride III-V compound semiconductor crystal and (0006) reflection of sapphire crystal.

16. A manufacturing method of a semiconductor device using a nitride III-V compound semiconductor layer grown on a sapphire substrate, comprising:

first forming recesses on a major surface of said sapphire substrate, and thereafter growing said nitride III-V compound semiconductor layer on said major surface of said sapphire substrate.

17. The manufacturing method of a semiconductor layer according to

claim 16

wherein at least a part of the inner surface of each said recess makes an angle not smaller than 10 degrees with respect to a major surface of said sapphire substrate nearer to said nitride III-V compound semiconductor layer.

18. The manufacturing method of a semiconductor device according to

claim 16

wherein said one major surface of the sapphire substrate nearer to the nitride III-V compound semiconductor layer includes surfaces inclined by a slight angle from the (0001) plane or the (0001) plane of sapphire crystal.

19. The manufacturing method of a semiconductor device according to

claim 16

wherein each said recess has a depth not less than 25 nm and a width not less than 30 nm.

20. The manufacturing method of a semiconductor device according to

claim 16

wherein said nitride III-V compound semiconductor layer is grown after first growing a buffer layer made of a nitride III-V compound semiconductor on said major surface of the sapphire substrate at a first temperature of the substrate temperature, and next raising the substrate temperature from said first temperature to a second temperature higher than said first temperature.

21. The manufacturing method of a semiconductor device according to

claim 16

wherein a buffer layer made of a nitride III-V compound semiconductor is grown on said sapphire substrate while raising the substrate temperature from a third temperature to a fourth temperature higher than said third temperature.

22. The manufacturing method of a semiconductor device according to

claim 16

wherein said nitride III-V compound semiconductor layer is grown directly on said sapphire substrate while raising the substrate temperature from a fifth temperature to a six temperature higher than said fifth temperature.

23. The manufacturing method of a semiconductor device according to

claim 21

wherein nitride III-V compound semiconductor crystal having a higher Al composition ratio than said nitride III-V compound semiconductor layer is made to at least plug said recesses of the sapphire substrate by crystallizing said buffer layer plugged inside said recesses of said sapphire substrate or improving crystalline property thereof and making Al diffuse from said sapphire substrate into said buffer layer by annealing while the substrate temperature is raised.

24. The manufacturing method of a semiconductor device according to

claim 22

wherein nitride III-V compound semiconductor crystal having a higher Al composition ratio than said nitride III-V compound semiconductor layer is made to at least plug said recesses of the sapphire substrate by crystallizing said buffer layer plugged inside said recesses of said sapphire substrate or improving crystalline property thereof and making Al diffuse from said sapphire substrate into said buffer layer by annealing while the substrate temperature is raised.

25. The manufacturing method of a semiconductor device according to

claim 23

wherein nitride III-V compound semiconductor crystal having a higher Al composition ratio than said nitride III-V compound semiconductor layer is made to at least plug said recesses of the sapphire substrate by crystallizing said nitride III-V compound semiconductor layer plugged inside said recesses of said sapphire substrate or improving crystalline property thereof and making Al diffuse from said sapphire substrate into said nitride III-V compound semiconductor layer by annealing while the substrate temperature is raised.

26. The manufacturing method of a semiconductor device according to

claim 23

wherein each said recess has a depth not less than 10 nm and a width not less than 30 nm.

27. The manufacturing method of a semiconductor device according to

claim 24

wherein each said recess has a depth not less than 10 nm and a width not less than 30 nm.

28. The manufacturing method of a semiconductor device according to

claim 25

wherein each said recess has a depth not less than 10 nm and a width not less than 30 nm.

29. The manufacturing method of a semiconductor device according to

claim 20

wherein said major surface of said sapphire substrate is nitrided prior to growth of said buffer layer.

30. The manufacturing method of a semiconductor device according to

claim 21

wherein said major surface of said sapphire substrate is nitrided prior to growth of said buffer layer.

31. The manufacturing method of a semiconductor device according to

claim 22

wherein said major surface of said sapphire substrate is nitrided prior to growth of said nitride III-V compound semiconductor layer.