Thin film transistor and method of fabricating the same

• US 20010010953A1
• Filed: 03/19/2001
• Published: 08/02/2001
• Est. Priority Date: 06/05/1998
• Status: Active Grant

• Current Assignee: LG Semicon Co Ltd (SK Hynix Inc.)
• Original Assignee: LG Semicon Co Ltd (SK Hynix Inc.)
• Inventors: Kang, Sung Gu, Jeon, Young Jun
• Granted Patent: US 6,455,357 B2
• Time in Patent Office: Days
• US Class Current: 438/158
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: Y10S 438/978 forming tapered edges on substrate or adjacent layers

Abstract

A thin film transistor is provided that includes a substrate, a gate electrode formed on the substrate, and a gate insulating layer formed all over the substrate including the gate electrode. A first semiconductor layer is formed on the gate insulating layer, and a second semiconductor layer is formed on the first semiconductor layer. Source and drain electrodes are separately etched together to expose a prescribed portion surface of the second semiconductor layer over the gate electrode. The source and drain electrodes adjacent to the prescribed portion of the second semiconductor layer are non-linearly inclined at their edges. A method of fabricating a thin film transistor includes forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode and the substrate, forming a first semiconductor layer on the gate insulating layer and forming a second semiconductor layer on the first semiconductor layer. First and second conductive materials are deposited on the second semiconductor layer. A single etching process is performed on the first and second conductive materials using the same etching gas to expose a prescribed part of the second semiconductor layer over the gate electrode to make the etched first and second conductive materials have a tier structure at edges of the prescribed part.

Claims

1. A thin film transistor, comprising:

a substrate;

a gate on the substrate;

a gate insulating layer on the substrate and the gate electrode;

a first semiconductor layer on the gate insulating layer;

a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer exposes a prescribed portion of the first semiconductor layer; and

first and second electrodes on the second semiconductor layer to expose the first and second semiconductor layers over the gate, wherein edges of the first and second electrodes adjacent to the exposed surface of the second semiconductor layer are non-linearly inclined.

2. The thin film transistor according to

claim 1

, wherein the first and second electrodes include a first conductive material and a second conductive material stacked on the first conductive material.

3. The thin film transistor according to

claim 2

, wherein the first and second conductive layers are etched concurrently in a single process using a single etchant to form source and drain electrodes.

4. The thin film transistor according to

claim 2

, wherein the first conductive material does not correspond to the second conductive material at the edges of the first and second electrodes, and wherein the first conductive material is chromium and the second conductive material is molybdenum.

5. The thin film transistor according to

claim 2

, wherein the second conductive material is thicker than the first conductive material, and wherein an etching ratio of the second conductive material to the first conductive material is approximately 10 to 1.

6. The thin film transistor according to

claim 1

, wherein the first semiconductor layer is an amorphous silicon layer, the second semiconductor layer is an n+ amorphous silicon layer and wherein the gate comprises:

a gate electrode patterned on the substrate; and

a gate insulating layer on the substrate and the gate electrode, wherein the gate electrode has a trapezoidal shape.

11. The film transistor according to

claim 6

, wherein etching the second conductive material is higher than etching the first conductive material in speed, and etching the first conductive material is higher than etching the second conductive material in speed.

12. The thin film transistor according to

claim 6

, wherein the first semiconductor layer is an amorphous silicon layer, the second semiconductor layer is an n+ amorphous silicon layer, the first conductive layer is chromium, and the second conductive layer is molybdenum, and wherein an etching ratio of the n+ amorphous silicon layer to the molybdenum is approximately 40 to 1.

19. The method according to

claim 12

, wherein the second and first conductive materials are etched to form source and drain electrodes, and wherein an etching selection ratio of the second conductive material to the first conductive material and the first conductive material to the second semiconductor layer is high, and wherein the first and second conductive materials have a tiered structure at edges of the prescribed part of the second semiconductive layer.

7. A thin film transistor, comprising:

a substrate;

a gate electrode on the substrate;

a gate insulating layer on the substrate and the gate electrode;

a first semiconductor layer on the gate insulating layer;

a second semiconductor layer on the first semiconductor layer on the gate electrode;

a first conductive material on the second semiconductor layer; and

a second conductive material on the first conductive material, wherein the first and second conductive materials expose the second semiconductor layer over the gate electrode, and wherein the first and second conductive materials have a tier structure to expose edges of the first conductive material.

8. The thin film transistor according to

claim 7

, wherein the first conductive material and the second conductive material are stacked to be source and drain electrodes.

9. The thin film transistor according to

claim 7

, wherein the first conductive material and the second conductive material are selectively removed at the same time using a single etchant.

10. The thin film transistor according to

claim 7

, wherein the edges of first conductive material do not correspond to the second conductive material.

13. A method of fabricating a thin film transistor comprising the steps of:

forming a trapezoidal shaped gate electrode on a substrate;

forming a gate insulating layer on the substrate and the gate electrode;

forming a first semiconductor layer on the gate insulating layer;

forming a second semiconductor layer on the first semiconductor layer;

depositing a first conductive material and a second conductive material on the second semiconductor layer; and

selectively etching the first conductive material and the second conductive material using a single etching gas to expose a prescribed part of the second semiconductor layer over the gate electrode, wherein respective edges of the etched first and second conductive materials are non-linearly inclined.

14. The method according to

claim 13

, wherein the selectively etching step is at least one of a reactive ion etching and a plasma etching, further comprising etching the second semiconductor layer over the gate electrode to expose the first semiconductor layer.

15. The method according to

claim 13

, wherein the single etching gas is Cl₂+O₂ gas.

16. The method according to

claim 15

, wherein the amount of the Cl₂ gas is approximately in the range of 400 to 600 sccm and the amount of the O₂ gas is approximately in the range of 300 to 500 sccm, and wherein the selectively removing step is performed under the pressure of 100 to 200 mTorr and RF power of 0.5 to 0.8 watts/cm².

17. The method according to

claim 13

, further comprising depositing a passivation layer wherein the respective edges of the etched first and second conductive materials are tiered to improve step coverage.

18. The method according to

claim 13

, wherein an etching selection ratio of the first conductive material to the gate insulating layer is high.