COMMUNICATION CHANNEL AND INTERFACE DEVICES FOR BRIDGING COMPUTER INTERFACE BUSES

• US 20010011312A1
• Filed: 09/08/1998
• Published: 08/02/2001
• Est. Priority Date: 05/01/1998
• Status: Active Grant

• Current Assignee: Acqis LLC (Acqis Technology, Inc.)
• Original Assignee: Acqis Technology, Inc.
• Inventors: CHU, WILLIAM W. Y.
• Granted Patent: US 6,345,330 B2
• Time in Patent Office: Days
• US Class Current: 710/64
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function

Abstract

The present invention encompasses an apparatus for bridging a first computer interface bus and a second computer interface bus, where each of the first and second computer interface buses have a number of parallel multiplexed address/data bus lines and operate at a clock speed in a predetermined clock speed range having a minimum clock speed and a maximum clock speed. The apparatus comprises an interface channel having a clock line and a plurality of bit lines for transmitting bits; a first interface controller coupled to the first computer interface bus and to the interface channel to encode first control signals from the first computer interface bus into first control bits to be transmitted on the interface channel and to decode second control bits received from the interface channel into second control signals to be transmitted to the first computer interface bus; and a second interface controller coupled to the interface channel and the second computer interface bus to decode the first control bits from the interface channel into third control signals to be transmitted on the second computer interface bus and to encode fourth control signals from the second computer interface bus into the second control bits to be transmitted on the interface channel.

In one embodiment, the first and second interface controllers comprise a host interface controller (HIC) and a peripheral interface controller (PIC), respectively, the first and second computer interface buses comprise a primary PCI and a secondary PCI bus, respectively, and the interface channel comprises an LVDS channel.

Claims

1. In a microprocessor based computer system, an apparatus for bridging a first computer interface bus and a second computer interface bus, each of the first and second computer interface buses having a number of parallel multiplexed address/data bus lines, each of said bus lines operating at a clock speed in a predetermined clock speed range having a minimum clock speed and a maximum clock speed, said apparatus comprising:

a first interface controller coupled to the first computer interface bus to encode control signals from the first computer interface bus into control bits;

an interface channel coupled to said first interface controller, said interface channel having a clock channel and a plurality of bit channels and transmitting said control bits from said first interface controller; and

a second interface controller coupled to said interface channel and the second computer interface bus, said second interface controller to decode said control bits from said interface channel into control signals to be transmitted on the second computer interface bus.

2. The apparatus of

claim 1

, wherein said first interface controller comprises a host interface controller (HIC) and said second interface controller comprises a peripheral interface controller (PIC).

3. The apparatus of

claim 2

, wherein said first computer interface bus comprises a primary peripheral component interconnect (PCI) bus within an attached computer module, said second computer interface bus comprises a secondary PCI bus within a peripheral console, and said interface channel comprises a low voltage differential signal (LVDS) channel, further wherein said HIC comprises a first PCI bus controller coupled to the primary PCI bus, a first translator coupled to said first PCI bus controller, a first transmitter coupled to said first translator, and a first receiver coupled to said first translator, further wherein said PIC comprises a second PCI bus controller coupled to the secondary PCI bus, a second translator coupled to said second PCI bus controller, a second transmitter coupled to said second translator, and a second receiver coupled to said second translator.

4. The apparatus of

claim 1

, wherein said interface channel comprises two sets of unidirectional lines.

5. The apparatus of

claim 4

, wherein each of said two sets of unidirectional lines comprises a point-to-point bus.

6. The apparatus of

claim 5

, wherein each of said two sets of unidirectional lines comprises a single master bus.

7. The apparatus of

claim 1

, wherein said interface channel further comprises a reset line.

8. The apparatus of

claim 1

, wherein said clock channel of said interface channel operates at a higher clock speed than the clock speed of the first and second computer interface buses.

9. The apparatus of

claim 1

, wherein said plurality of bit channels are fewer in number than both the number of multiplexed address/data bus lines in said first computer interface bus and the number of multiplexed address/data bus lines in said second computer interface bus.

10. In a computer system having a primary peripheral component interconnect (PCI) bus, a secondary PCI bus, and an interface channel interfacing said primary and secondary PCI buses, each of the primary and secondary PCI buses having a number of parallel multiplexed address/data lines, each of said bus lines operating at a clock speed in a predetermined clock speed range having a minimum clock speed and a maximum clock speed, an interface controller comprising:

a bus controller to interface with one of the primary and secondary PCI buses and to manage transactions that occur with said one of the primary and secondary PCI buses; and

a translator coupled to said bus controller to encode control signals from said one of the primary and secondary PCI buses into control bits and to decode control bits from the interface channel into control signals.

11. The interface controller of

claim 10

further comprising:

a transmitter coupled to said translator, wherein said transmitter serializes parallel bits into first serial bit packets and transmits said first serial bit packets to the interface channel; and

a receiver coupled to said translator, wherein said receiver receives second serial bit packets from said interface channel and recovers parallel bits from said second serial bit packets.

12. The interface controller of

claim 11

further comprising a reset control circuit for one of sending a reset signal to and receiving a reset signal from a second interface controller.

13. The interface controller of

claim 11

further comprising a reset and parity error circuit for sending a parity error signal and a reset signal.

14. The interface controller of

claim 11

further comprising a video parallel to serial converter to receive video capture data, including video port control signals and parallel video port data, convert said video port control signals and said parallel video port data into serial video data and transmit said serial video data to a second interface controller.

15. The interface controller of

claim 11

further comprising a video serial to parallel converter to receive serial video data on a video data line, convert said serial video data to video port control signals and parallel video port data, and transmit said video port control signals and said parallel video port data to a graphics controller.

16. An interface device for interfacing a first peripheral component interconnect (PCI) bus of a first computer system with a second PCI bus of a second computer system, said interface device comprising:

a first connector for coupling to the first PCI bus;

a second connector for coupling to the second PCI bus; and

a cable coupled to said first and second connectors, wherein said cable comprises an interface channel including a clock channel on a pair of conductive lines and a plurality of bit channels on a plurality of pairs of conductive lines, for transferring information between said first and second connectors using low voltage differential signals (LVDS).

17. The interface device of

claim 16

, wherein said interface channel comprises a first subset of channels, including a first clock channel on a first pair of conductive lines and a first plurality of bit channels on a first plurality of pairs of conductive lines, for transferring information from said first connector to said second connector and a second subset of channels, including a second clock channel on a second pair of conductive lines and a second plurality of bit channels on a second plurality of pairs of conductive lines, for transferring information from said second connector to said first connector.

18. In a computer system including an attached computer module (ACM) and a peripheral console, an interface device for interfacing a primary peripheral component interconnect (PCI) bus of the ACM to a secondary PCI bus of the peripheral console, said interface device comprising:

a first connector for coupling to the primary PCI bus;

a second connector for coupling to the secondary PCI bus; and

an interface channel coupled to said first and second connectors, said interface channel including a clock channel and a plurality of bit channels, wherein said clock channel and said plurality of bit channels are on a plurality of conductive lines and further wherein information is transferred on said interface channel using a protocol different from that of a PCI bus.

19. The interface device of

claim 18

further comprising a cable comprising said interface channel, wherein information is transferred between said first and second connectors using low voltage differential signals (LVDS) and further wherein said interface channel comprises a first subset of channels, including a first clock channel on a first pair of conductive lines and a first plurality of bit channels on a first plurality of pairs of conductive lines, for transferring information from said first connector to said second connector and a second subset of channels, including a second clock channel on a second pair of conductive lines and a second plurality of bit channels on a second plurality of pairs of conductive lines, for transferring information from said second connector to said first connector.

20. An apparatus for interfacing first and second subsystems of a microprocessor based computer system, said apparatus comprising:

a first computer interface bus within said first subsystem, said first computer interface having a first number of parallel multiplexed address/data bus lines, wherein each of said bus lines in said first computer interface bus operates at a clock speed in a first predetermined clock speed range bounded by a first minimum clock speed and a first maximum clock speed and further wherein each of said bus lines in said first computer interface bus transmits bits in a first predetermined bit rate range bounded by a first minimum per line bit rate and a first maximum per line bit rate;

a second computer interface bus within said second subsystem, said second computer interface having a second number of parallel multiplexed address/data bus lines, wherein each of said bus lines in said second computer interface bus operates at a clock speed in a second predetermined clock speed range bounded by a second minimum clock speed and a second maximum clock speed and further wherein each of said bus lines in said second computer interface bus transmits bits in a second predetermined bit rate range bounded by a second minimum per line bit rate and a second maximum per line bit rate; and

an interface channel including a clock channel and a plurality of bit channels, wherein said plurality of bit channels are fewer in number than both said first number and said second number.

21. The apparatus of

claim 20

, wherein each of said plurality of serial bit channels operates at a clock speed higher than both said first maximum clock speed and said second maximum clock speed.

22. The apparatus of

claim 20

, wherein each of said plurality of serial bit channels transmits bits at a bit rate higher than said first maximum per line bit rate and said second maximum per line bit rate.

23. An apparatus for interfacing first and second subsystems of a microprocessor based computer system, said apparatus comprising:

a first computer interface bus within said first subsystem, said first computer interface having a first number of parallel multiplexed address/data bus lines, wherein each of said bus lines in said first computer interface bus operates at a clock speed in a first predetermined clock speed range bounded by a first minimum clock speed and a first maximum clock speed;

a second computer interface bus within said second subsystem, said second computer interface having a second number of parallel multiplexed address/data bus lines, wherein each of said bus lines in said second computer interface bus operates at a clock speed in a second predetermined clock speed range bounded by a second minimum clock speed and a second maximum clock speed; and

an interface channel including a clock channel and a plurality of serial bit channels, wherein each of said plurality of serial bit channels operates at a clock speed higher than both said first maximum clock speed and said second maximum clock speed.

24. In a computer system having an attached computer module (ACM) and a peripheral console, an apparatus for interfacing the ACM and the peripheral console, said apparatus comprising:

a first control signal based computer interface bus within the ACM;

a bit based interface channel coupled to said first control signal based computer interface bus; and

a second control signal based computer interface bus within the peripheral console, said second control signal based computer interface bus coupled to said bit based interface channel.

25. A computer system comprising:

an attached computer module (ACM) including a first control based computer interface bus;

a peripheral console including a second control based computer interface bus; and

a bit based interface channel coupled to said first control signal based computer interface bus and said second control based computer interface device for interfacing said ACM and said peripheral console.

26. The computer system of

claim 25

, wherein said first control based computer interface bus comprises a host peripheral component interconnect (PCI) bus including a first number of bus lines, operating at a first clock speed, and transferring bits at a first per line bit rate and said second control based computer interface bus comprises a secondary PCI bus having a second number of bus lines, operating at a second clock speed, and transferring bits at a second per line bit rate.

27. The computer system of

claim 26

, wherein said bit based interface channel comprises a clock channel and a plurality of bit channels.

28. The computer system of

claim 27

, wherein said bit based interface channel comprises a first set of unidirectional channels including a first clock channel and a first plurality of bit channels and a second set of unidirectional channels including a second clock channel and a second plurality of bit channels.

29. The computer system of

claim 28

, wherein said first and second sets of unidirectional channels comprise low voltage differential signal (LVDS) lines.

30. The computer system of

claim 27

, wherein said interface channel operates at a clock speed higher than said first and second clock speeds.

31. The computer system of

claim 27

, wherein each bit channel in said interface channel transfers bits at a bit rate higher than said first and second per line bit rates.

32. The computer system of

claim 27

, wherein said plurality of bit channels is smaller in number than both said first number of bus lines and said second number of bus lines.

33. The computer system of

claim 26

, wherein said interface channel consists of one clock channel and one bit channel.

34. The computer system of

claim 33

, wherein said interface channel is a IEEE 1394 bus.

35. The computer system of

claim 25

, wherein said first and second computer interface buses each comprise at least 32 bus lines.

36. The computer system of

claim 25

further comprising a video bus for transferring video capture data from said peripheral console to said ACM.

37. The computer system of

claim 25

further comprising a video bus for transmitting digital video signals from said ACM to said peripheral console.

38. The computer system of

claim 37

, wherein said video bus comprises a bus for transmitting video signals for flat panel displays from said ACM to said peripheral console.

39. The computer system of

claim 25

further comprising a video bus for transmitting television (TV) signals from said ACM to said peripheral console.

40. The computer system of

claim 25

further comprising a video bus for transmitting super video signals from said ACM to said peripheral console.

41. The computer system of

claim 25

further comprising a power bus for transmitting power at a plurality of voltage levels between said peripheral console and said ACM.

42. A method of transmitting control signals from a first computer interface bus to a second computer interface bus via a bit based interface channel coupled to the first computer interface bus and the second computer interface bus, said method comprising:

receiving control signals from the first computer interface bus;

encoding the control signals received from the first computer interface bus into control bits representing the control signals;

transmitting the control bits on the bit based interface channel;

receiving the control bits;

decoding the control bits into the control signals represented by the control bits; and

transmitting the control signals to the second computer interface bus.