Pixel structure with improved charge transfer

• US 20010011736A1
• Filed: 12/13/2000
• Published: 08/09/2001
• Est. Priority Date: 12/14/1999
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Dierickx, Bart
• Granted Patent: US 7,199,410 B2
• Time in Patent Office: Days
• US Class Current: 257/218
• CPC Class Codes: H01L 27/1443 with at least one potential jump or surface barrier
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14812 Special geometry or disposition of pixel-elements, address lines or gate-electrodes
• CPC Class Codes: H01L 31/0352 characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
• CPC Class Codes: H04N 25/531 by controlling rolling shutters in CMOS SSIS
• CPC Class Codes: H04N 25/585 with pixels having different sensitivities within the sensor, e.g. fast or slow pixels or pixels having different sizes
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

An active pixel is described comprising a semiconductor substrate and a radiation sensitive source of carriers in the substrate, such as for instance, a photodiode. A non-carrier storing, carrier collecting region in the substrate is provided for attracting carriers from the source as they are generated. At least one doped or inverted region of a first conductivity is provided in or on the substrate for storing the carriers before read-out. At least one non-carrier storing, planar current flow, carrier transport pathway is provided from or through the carrier collecting region to the at least one doped or inverted region to transfer the carriers without intermediate storage to the read-out electronics.

Claims

1. An pixel structure comprising:

a semiconductor substrate;

a radiation sensitive source of carriers in the substrate;

a non-carrier storing, carrier collecting region in the substrate;

at least one doped or inverted region of a first conductivity in or on the substrate; and

a least one non-carrier storing, planar current flow, carrier transport pathway from or through the carrier collecting region to the at least one doped or inverted region.

2. The pixel structure according to

claim 1

, wherein the non-carrier storing, carrier collecting region has a concentration so low that it is in normal use always depleted.

3. The pixel structure according to

claim 2

, wherein at least part of the non-carrier storing, carrier collecting region is a pinned or buried diode.

4. The pixel structure according to

claim 1

, wherein the non-carrier storing, carrier collecting region is substrate under a covering oxide layer.

5. The pixel structure according to

claim 1

, wherein the non-carrier storing, carrier collecting region is substrate under a field oxide layer.

6. The pixel structure according to

claim 1

, wherein the non-carrier storing, carrier collecting region is substrate under a polysilicon cover layer.

7. The pixel structure according to

claim 1

, wherein the non-carrier storing, carrier transport region is diffusion limited.

8. The pixel structure according to

claim 1

, further comprising at least one implant confining the carrier collecting region along at least one dimension thereof.

9. The pixel structure according to

claim 1

, further comprising regions of a second conductivity type in or on the substrate avoiding touching of the carrier collecting region and a field oxide.

10. The pixel structure according to

claim 1

, wherein the pixel is MOS-based.

11. A pixel array comprising at least one set of pixels of a first sensitivity and at least a second set of pixels of a second sensitivity, the first and second sensitivities being different from each other.

12. A pixel array comprising a plurality of pixel structures, each pixel structure comprising:

a photosensitive element for converting radiation into charge carriers;

a carrier storing element;

a first switch located in-between said photosensitive element and said carrier storing element; and

said photosensitive element also being connected to a voltage with a reset switch;

and the pixel array further comprising;

a timing circuit for resetting all the pixels of the array simultaneously.

13. A pixel array according to

claim 12

, wherein the carrier storing element of at least one pixel is an analog memory element such as a capacitor or a parasitic capacitor.

14. A pixel array according to

claim 12

, wherein each pixel is MOS-based.

15. A pixel array according to

claim 12

, further comprising an amplifier connected to each carrier storing element.

16. A pixel array according to

claim 15

, wherein an amplifier is located within at least one pixel structure to have an active pixel.

17. A pixel array according to

claim 15

, wherein an amplifier is placed outside at least one pixel structure to obtain a passive pixel.

18. A pixel array comprising a plurality of pixels, each pixel comprising:

a photosensitive element for converting radiation into charge carriers;

a carrier storing element;

a first switch located in-between said photosensitive element and said carrier storing element; and

said photosensitive element also being connected to a voltage with a reset switch;

and the pixel array further comprising;

a timing circuit for simultaneously opening the first switches of all the pixels of the array simultaneously.

19. A pixel array according to

claim 18

, wherein the carrier storing element of at least one pixel is an analog memory element such as a capacitor or a parasitic capacitor.

20. A pixel array according to

claim 18

, wherein each pixel is MOS-based.

21. A pixel array according to

claim 18

, further comprising an amplifier connected to each carrier storing element.

22. A pixel array according to

claim 21

, wherein an amplifier is located within at least one pixel structure to have an active pixel.

23. A pixel array according to

claim 21

, wherein an amplifier is placed outside at least one pixel structure to obtain a passive pixel.

24. A range pixel comprising:

a semiconductor substrate;

a radiation sensitive source of carriers in the substrate;

a non-carrier storing, carrier collecting region in the substrate;

at least two doped or inverted regions of a first conductivity type in or on the substrate; and

a non-carrier storing, planar current flow, carrier transport pathway from or through the carrier collecting region to each doped or inverted region.