Voltage regulator circuit built in a semiconductor memory device

• US 20010012219A1
• Filed: 01/19/2001
• Published: 08/09/2001
• Est. Priority Date: 02/03/2000
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Byeong-Hoon, Lee, Seung-Keun
• Granted Patent: US 6,442,079 B2
• Time in Patent Office: Days
• US Class Current: 365/189.09
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

A voltage regulator circuit is disclosed which generates an output voltage obtained by adjusting a high voltage and has serially connected regulators of a two-stage structure. A regulator of a previous regulator adjusts the high voltage to a sufficiently constant voltage. A regulator of a next stage has a depletion-type NMOS transistor, and adjusts the high voltage to a voltage of a required level using a voltage adjusted by the regulator of the previous stage. According to this structure, an output voltage of the prevent voltage regulator circuit is clamped exactly at a voltage, which is identical to a sum of an absolute value of a threshold voltage of the depletion-type transistor and a voltage adjusted by the regulator of the previous stage, without overshooting over a required voltage level.

Claims

1. A voltage regulator circuit connected to a voltage booster for generating a high voltage VPP and having an output terminal for delivering a regulated output voltage VPPi, the voltage regulator comprising:

first means for receiving the high voltage VPP to produce a sufficiently constant voltage V1; and

second means including a driver, which is coupled between the high voltage and the output terminal, wherein the second means clamps the high voltage into the regulated output voltage which is such a voltage (V1+Vth) that the sufficiently constant voltage V1 is summed with a threshold voltage Vth of the driver.

2. The voltage regulator circuit according to

claim 1

, wherein the driver comprises a depletion-type MOS transistor which has a first current electrode coupled to the high voltage, a second current electrode coupled to the output terminal and a control electrode coupled to receive the sufficiently constant voltage;

and wherein the depletion-type MOS transistor is shut off when the adjusted output voltage reaches the voltage (V1+Vth).

3. The voltage regulator circuit according to

claim 2

, wherein the first means comprises:

a second depletion-type MOS transistor having a first current electrode coupled to receive the high voltage, a second current electrode coupled to the control electrode of the first depletion-type MOS transistor, and a control electrode coupled to receive a reference voltage; and

a switch coupled between the second current electrode of the second depletion-type MOS transistor and a ground voltage, the switch being switched according to a boost enable signal.

4. The voltage regulator circuit according to

claim 3

, wherein the first means further comprises a load coupled between the second depletion-type MOS transistor and the switch.

5. The voltage regulator circuit according to

claim 1

, wherein the first means comprises:

a first PMOS transistor having a first current electrode coupled to receive the high voltage, a second current electrode coupled to a ground voltage via a first NMOS transistor which is switched according to a reference voltage, and a control electrode coupled to the second current electrode of the first PMOS transistor;

a second PMOS transistor having a first current electrode coupled to receive the high voltage, a second current electrode coupled to the control electrode of the depletion-type MOS transistor, and a control electrode coupled to the control electrode of the first PMOS transistor; and

a second NMOS transistor having a first current electrode and a control electrode coupled to the control electrode of the depletion-type MOS transistor, and a second current electrode coupled to the ground voltage,

wherein the sufficiently constant voltage V1 is out from the second current electrode of the second PMOS transistor.

6. The voltage regulator circuit according to

claim 1

, wherein the first means comprises:

a first PMOS transistor having a first current electrode coupled to receive the high voltage, a second current electrode coupled to a ground voltage via a first NMOS transistor which is switched according to a reference voltage, and a control electrode coupled to the second current electrode of the first PMOS transistor;

a second PMOS transistor having a first current electrode coupled to receive the high voltage, a second current electrode coupled to the control electrode of the depletion-type MOS transistor, and a control electrode coupled to the control electrode of the first PMOS transistor; and

a resistor coupled between the second current electrode of the second PMOS transistor and the ground voltage,

wherein the sufficiently constant voltage V1 is out from the second current electrode of the second PMOS transistor.

7. A semiconductor memory device comprising:

an array of memory cells arranged in rows and columns;

a row decoder for selecting one of the rows; and

a word line voltage generating circuit for generating a word line voltage to be supplied to the selected row,

wherein the word line voltage generating circuit includes a voltage booster for generating a high voltage;

means for receiving the high voltage to produce a sufficiently constant voltage; and

a depletion-type MOS transistor coupled between the high voltage and the row decoder.

8. The voltage regulator circuit according to

claim 8

, wherein the depletion-type MOS transistor is shut off when the word line voltage reaches such a required voltage value that a value of the sufficiently constant voltage is summed with an absolute value of a threshold voltage of the depletion-type MOS transistor.

9. A voltage regulator circuit connected to a voltage booster for generating a high voltage VPP over a power supply voltage and having an output terminal for delivering a regulated output voltage VPPi, the voltage regulator comprising:

a first regulator for adjusting the high voltage VPP to output a sufficiently constant voltage V1 lower than the adjusted output voltage VPPi; and

a second regulator for adjusting the high voltage VPP according to the sufficiently constant voltage V1 to output the adjusted output voltage.

10. The voltage regulator circuit according to

claim 9

, wherein the second regulator comprises a depletion-type NMOS transistor, the depletion-type NMOS transistor having a drain connected to the high voltage, a source connected to the output terminal and a gate connected to receive the sufficiently constant voltage.