BALL GRID PACKAGE WITH MULTIPLE POWER/ GROUND PLANES

• US 20010013654A1
• Filed: 12/22/1999
• Published: 08/16/2001
• Est. Priority Date: 12/31/1998
• Status: Active Grant

• Current Assignee: Natural Compounds Ltd (Biosign Technologies, Inc.), Texas Instruments, Inc.
• Original Assignee: Natural Compounds Ltd (Biosign Technologies, Inc.)
• Inventors: KALIDAS, NAVINCHANDRA, THOMPSON, RAYMOND W, MURTUZA, MASOOD
• Granted Patent: US 6,396,136 B2
• Time in Patent Office: Days
• US Class Current: 257/738
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/07802 not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A package 300 for a flip chip integrated 331 circuit including an interposer 303 with electrical interconnecting for signal, power, and ground contacts. Routing is accomplished on only two conductor layers through the use of selective planes and buses. Multiple power planes are provided on a single conductor level to support circuits having different operating voltages. A unique cavity down BGA package for a flip chip interconnected integrated circuit is provided by adhering the interposer to a thermally conductive stiffener or base 304, and using solder balls 308 to attach the frame to the base and interposer. The assemblage forms a chip cavity with interconnecting vias to external BGA solder balls terminals located in the perimeter frame.

Claims

1. A cavity down ball grid array (BGA) package for a flip chip interconnected integrated circuit including;

a) a planar stiffener or package base,

b) an interposer circuit having a first surface bearing a first patterned conductive layer separated by a dielectric layer from a second patterned conductive layer, wherein the second surface is adhered to said stiffener by an insulating adhesive, and the first conductive surface includes a plurality of contact pads aligned to the flip chip connectors, and electrical interconnections to an array of input/output contact pads near the interposer perimeter,

c) solder bumps on each contact of said array of input/output contact pads near the interposer perimeter,

d) a frame positioned with the outer edge vertically aligned to the outer edge of said stiffener, and said frame having a first surface aligned to and connecting the array of solder bumps near the perimeter of the interposer circuit to conductive vias through the frame core to external BGA solder ball contacts on the second surface of the frame,

e) an underfill material surrounding the flip chip bumps and the frame solder bump connectors, and

f) an encapsulating compound which fills cavity formed by the frame and stiffener.

4. A cavity down BGA package as in

claim 1

wherein electrical interconnections for signal, power, and ground contacts is patterned on two conductor layers including selective planes and buses with specific boundaries for multiple power and ground planes.

5. A cavity down BGA package as in

claim 1

wherein the first patterned conductor layer of said interposer circuit includes one or more power planes and buses.

6. A cavity down BGA package as in

claim 1

the second patterned conductive layer of said interposer circuit includes a ground plane.

7. A cavity down BGA as in

claim 5

wherein a power plane is disposed in the center of the first patterned conductor layer and is bused to each corner of the interposer circuit.

8. A cavity down BGA package as in

claim 5

wherein one or more power planes are disposed in the first patterned layer of the interposer circuit between routing interconnections to external contacts.

9. A cavity down BGA package as in

claim 1

wherein the interposer circuit includes conductive vias connecting specific contacts between the first patterned conductor layer and the second patterned conductor layer.

10. A cavity down BGA package as in

claim 1

wherein the stiffener dissipates heat from the circuit to the atmosphere, or to a secondary heat spreader.

11. A cavity down BGA package as in

claim 1

wherein said frame is thicker than the integrated circuit.

12. A cavity down BGA package as in

claim 1

having solder bump connections between the interposer circuit and frame of similar size and composition as those of the flip chip solder bump connectors.

13. A cavity down BGA package as in

claim 1

wherein said interposer comprises a flex circuit.

14. A cavity down BGA package as in

claim 1

wherein said interposer comprises a BT resin core.

15. A cavity down BGA package as in

claim 1

wherein said frame comprises FR-4 resin.

16. A cavity down BGA package as in

claim 14

wherein said frame comprises a BT resin core.

18. A cavity down BGA as in

claim 1

wherein a first power plane is disposed in the center of the first patterned conductor layer and bused to each corner of the interposer circuit, and additional power planes are disposed between routing interconnections to external contacts in the first patterned conductor layer.

2. A cavity down ball grid array (BGA) package for a flip chip interconnected integrated circuit chip including;

a) a planar stiffener or package base,

b) an interposer circuit having conductive traces on the first surface including a plurality of contact pads aligned to the flip chip connectors, and electrical interconnections to an array of input/output contact pads near the interposer perimeter, and the second surface of the interposer is adhered to said stiffener by an insulating adhesive,

c) solder bumps on each contact of said array of input/output contact pads near the interposer perimeter,

d) a frame positioned with the outer edge vertically aligned to the outer edge of said stiffener, and said frame having a first surface aligned to and connecting the array of solder bumps near the perimeter of the interposer circuit to conductive vias through the frame core to external BGA solder ball contacts on the second surface of the frame,

e) an underfill material surrounding the flip chip bumps, and the frame solder bump connectors, and

f) an encapsulating compound which fills cavity formed by the frame and stiffener.

3. A semiconductor package having an interposer circuit comprising two conductive layers separated by a dielectric layer, wherein electrical interconnection for signal, power and ground contacts is patterned on the two conductor layers including selective planes and buses with specific boundaries providing multiple power and ground planes.

19. A semiconductor package as in

claim 3

wherein the first patterned conductor layer of the interposer includes one or more power planes.

17. A cavity down ball grid array (BGA) package for a flip chip interconnected integrated circuit including;

a) a planar stiffener or package base which dissipates heat from the circuit to the atmosphere, or to a secondary heat spreader,

b) an interposer circuit comprising two patterned conductor layers separated by a dielectric layer, wherein electrical routing for signal, power and ground contacts is patterned on the two conductor layers, including selective planes and buses with specific boundaries to form one or more power planes, the first conductor layer includes a plurality of contact pads in the central area aligned to the flip chip connectors electrically interconnecting to an a array of input/output contact pads near the interposer perimeter and a ground plane is included on the second conductor layer, and wherein conductive vias provide interconnection between specific contacts on the first and second conductor layers, and wherein the second surface is adhered to said stiffener by an insulating adhesive, and p1 c) an array of solder bumps of similar size and composition to the flip chip connectors, disposed on each of the input/output contact pads near the interposer perimeter,

d) a frame of greater thickness than said integrated circuit chip, positioned with the outer edge vertically aligned to the outer edge of the stiffener, and having a first surface aligned to and connecting the solder bumps of on the interposer perimeter to conductive vias through the frame core to external BGA solder ball contacts on the second surface of the frame,

d) an underfill material surrounding the flip chip bumps, and the frame solder bump connectors, and

e) an encapsulating compound which fills cavity formed by the frame and stiffener.

20. A cavity up BGA package having an interposer circuit wherein electrical routing for signal, power and ground contacts is accomplished on two conductor layers including selective planes and buses with specific boundaries to provide multiple power and ground planes.