Data storage unit with cyclic error detection and avoidance

• US 20010016884A1
• Filed: 02/14/2001
• Published: 08/23/2001
• Est. Priority Date: 07/24/1997
• Status: Abandoned Application

• Current Assignee: Atsushi Kanamaru, Hideo Asano, Hiroshi Oshikawa, Masahiko Sato, Toshio Kakihara
• Original Assignee: Atsushi Kanamaru, Hideo Asano, Hiroshi Oshikawa, Masahiko Sato, Toshio Kakihara
• Inventors: Sato, Masahiko, Oshikawa, Hiroshi, Kakihara, Toshio, Asano, Hideo, Kanamaru, Atsushi
• Application Number:
  US09/784,538
• Publication Number:
  US 20010016884A1
• Time in Patent Office: Days
• US Class Current: 710/29
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0676 Magnetic disk device

Abstract

Methods and apparatus are described for a data transfer unit between a storage unit and a host, wherein a slower data transfer rate is established when a predetermined error is detected. In one embodiment the cyclicity of the error occurrence calculated and a wait is inserted between data to avoid transferring data at the calculated cyclicity point of the detected error. Optionally the data transfer unit may return the data transfer rate to the original data transfer rate or state after a predetermined time has elapsed, after a predetermined number of commands have been received, after a predetermined amount of data have been transferred, or by combination of these.

Claims

1. A data transfer unit for transferring data in a direct memory access (DMA) transfer mode between a storage unit and a host, comprising:

data transfer means for transferring data at one of at least first and second data transfer rates where the second data transfer rate is slower than the first data transfer rate;

error detection means for detecting a predetermined error in transferring the data; and

control means for transferring data between the storage unit and the host at the first data transfer rate until the predetermined error is detected by the error detection means whereupon the data is temporarily transferred at the second data transfer rate until a specified event occurs.

2. The data transfer unit of

claim 1

, further comprising means for returning a data transfer rate to the first data transfer rate when the specified event occurs and wherein the specified event includes that a predetermined time has elapsed while transferring data at the second rate.

3. The data transfer unit of

claim 1

, further comprising means for returning a data transfer rate to the first data transfer rate when the specified event occurs and wherein the specified event includes that a predetermined number of commands have been received while transferring data at the second rate.

4. The data transfer unit of

claim 1

, further comprising means for returning a data transfer rate to the first data transfer rate when the specified event occurs and wherein the specified event includes that a predetermined amount of data has been transferred while transferring data at the second rate.

5. The data transfer unit as set forth in

claim 1

, wherein the DMA transfer mode is based upon an Ultra DMA transfer mode.

6. The data transfer unit as set forth in

claim 1

further comprising:

calculation means for calculating cyclicity of a plurality of predetermined error occurrences; and

control means for inserting a predetermined wait to avoid transferring data at the cyclicity of the plurality of predetermined error occurrences.

7. A method of transferring data between a storage unit and a host, comprising the steps of:

setting a first data transfer rate;

transferring data between the storage unit and the host at the first data transfer rate;

detecting an error in the transferred data;

setting the data transfer rate to a second data transfer rate slower than the first data transfer rate when a predetermined error is detected in the step of detecting an error; and

transferring data between the storage unit and the host at the second transfer rate.

8. The method of

claim 7

further comprising the steps of:

calculating cyclicity of a plurality of predetermined errors; and

inserting a predetermined wait in the data to avoid transferring data at the calculated cyclicity of the plurality of predetermined errors.

9. The method of

claim 7

, further comprising the step of returning a data transfer rate to the first data transfer rate when a specified condition occurs and wherein the specified condition includes that a predetermined number of commands have been received while transferring data at the second rate.

10. The method of

claim 7

, further comprising the step of returning a data transfer rate to the first data transfer rate when the specified condition occurs and wherein the specified condition includes that a predetermined amount of data has been transferred while transferring data at the second rate.

11. A data transfer unit for transferring data between devices, comprising:

error detection means for detecting a plurality of errors while transferring data;

calculation means for calculating cyclicity of the plurality of errors; and

control means for performing control so that data transfer avoids the calculated cyclicity of the detected error occurrence, based on an output of the calculation means.

12. The data transfer unit of

claim 11

wherein the control means inserts wait bits into the data stream to avoid the calculated cyclicity.

13. The data transfer unit of

claim 11

further comprises means for returning to an original state upon a condition which includes that a predetermined number of commands have been received while avoiding the calculated cyclicity.

14. The data transfer unit of

claim 11

further comprises means for returning to a original state upon a condition which includes that predetermined time has elapsed while avoiding the calculated cyclicity.

15. The data transfer unit of

claim 11

further comprises means for returning to a original state upon a condition which includes that predetermined amount of data has been transferred while avoiding the calculated cyclicity.