Integrated network switching hub and bus structure
First Claim
1. An integrated circuit (IC) switching hub, comprising:
- a parallel bus of n bus lines implemented as traces on the IC;
a first data port adapter controller connected by n first port lines through a first output buffer to the bus, each first port line connected to a bus line source-to-drain through one of a set of first queue switch transistors, and connected to a first data port providing a first external data link for the switching hub;
a first read amplifier connected by n first receiver lines one each directly to each one of the n bus lines, and by a first data link to the first port adapter controller;
a second data port adapter controller connected by n second port lines through a second output buffer to the bus, each second port line connected to a bus line source-to-drain through one of a set of second queue switch transistors, and connected to a second data port providing a second external data link for the switching hub;
a second read amplifier connected by n second receiver lines one each directly to each one of the n bus lines and by a second data link to the second port adapter controller; and
an arbitrator controller connected by a first control line to the gates of the first set of queue switch transistors, by a second control line to the gates of the second set of queue switch transistors, by a third control line to the first port adapter controller, and by a fourth control line to the second port adapter controller;
wherein the arbitrator controller is adapted to switch data from the first and second port adapter controllers onto the bus through the first and second output buffers and the first and second sets of queue switch transistors by switching the gates of the transistors via the first and second control lines respectively, and adapted to transfer data from the bus to the first and second external data links via the first and second read amplifiers through the first and second port adapter controllers by enabling the respective port adapter controllers via the third and fourth control lines respectively, according to a preprogrammed arbitration scheme.
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Accused Products
Abstract
A network switching hub is implemented on an IC chip, and has a bus connected to external ports through sets of que switch transistors, source to drain for data switched onto the bus, the queue switch transistors gated simultaneously by control lines from an on-board arbitrator controller following a preprogrammed arbitration scheme. Data is switched off the bus and hub by port adapter controllers connected to read amplifier receivers connected directly to the on-chip bus, the port adapter controllers enabled by the arbitrator controller following the same preprogrammed arbitration scheme. Ports may be serial or parallel, and may be adapted to special purposes, such as PCI and hub to hub connection for expansion.
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Citations
8 Claims
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1. An integrated circuit (IC) switching hub, comprising:
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a parallel bus of n bus lines implemented as traces on the IC;
a first data port adapter controller connected by n first port lines through a first output buffer to the bus, each first port line connected to a bus line source-to-drain through one of a set of first queue switch transistors, and connected to a first data port providing a first external data link for the switching hub;
a first read amplifier connected by n first receiver lines one each directly to each one of the n bus lines, and by a first data link to the first port adapter controller;
a second data port adapter controller connected by n second port lines through a second output buffer to the bus, each second port line connected to a bus line source-to-drain through one of a set of second queue switch transistors, and connected to a second data port providing a second external data link for the switching hub;
a second read amplifier connected by n second receiver lines one each directly to each one of the n bus lines and by a second data link to the second port adapter controller; and
an arbitrator controller connected by a first control line to the gates of the first set of queue switch transistors, by a second control line to the gates of the second set of queue switch transistors, by a third control line to the first port adapter controller, and by a fourth control line to the second port adapter controller;
wherein the arbitrator controller is adapted to switch data from the first and second port adapter controllers onto the bus through the first and second output buffers and the first and second sets of queue switch transistors by switching the gates of the transistors via the first and second control lines respectively, and adapted to transfer data from the bus to the first and second external data links via the first and second read amplifiers through the first and second port adapter controllers by enabling the respective port adapter controllers via the third and fourth control lines respectively, according to a preprogrammed arbitration scheme. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for switching data on to a bus of an integrated circuit switching hub, the bus having n bus lines, comprising steps of:
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(a) receiving data at an external port of the switching hub, and transferring the data to a port adapter controller;
(b) connecting the port adapter controller to the bus by n data lines through a set of n queue switch transistors connecting the n lines to the n bus lines source-to-drain;
(c) switching data on to the bus by gating the set of queue switch transistors simultaneously by command of an on-chip arbitrator controller.
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Specification