Deep trace memory system for a protocol analyzer

• US 20010016925A1
• Filed: 05/03/2001
• Published: 08/23/2001
• Est. Priority Date: 11/17/1997
• Status: Active Grant

• Current Assignee: Viavi Solutions, Inc. (Lumentum Holdings Inc.)
• Original Assignee: I-Tech Corporation (II-VI Incorporated)
• Inventors: Wall, Timothy A., Kuechle, Daniel G., Bucher, Steven
• Granted Patent: US 6,393,587 B2
• Time in Patent Office: Days
• US Class Current: 714/39
• CPC Class Codes: H04L 43/18 Protocol analysers
• CPC Class Codes: Y10S 707/99936 Pattern matching access

Abstract

A deep trace buffer management system for a protocol analyzer includes a hardware search engine that locates specified data patterns within the trace buffer as directed by a host processor. The protocol analyzer is preferably connected to a laptop computer that serves as the host processor, and the protocol analyzer preferably is housed in a portable chassis separate from the host processor and has a host port to connect to the host processor through a relatively small bandwidth port. An interface port connects the protocol analyzer to the communication interface under analysis. Logic circuitry controls selective read and write operations of traces to and from the trace buffer in response to parameters as directed by the host processor.

Claims

1. A protocol analyzer having a deep trace memory system that stores traces captured from a communication interface for presentation by a host processor, the protocol analyzer comprising:

a portable chassis physically separate from the host processor that includes;

a host port that provides a connection to the host processor;

an interface port that provides a connection to the communication interface;

a trace buffer memory;

logic circuitry that controls selective write operations of traces from the interface port to the trace buffer and selective read operations of traces from the trace buffer to the host port in response to parameters directed by the host processor; and

a hardware search engine that locates specified data patterns as directed by the host processor within the trace buffer.

2. The protocol analyzer of

claim 1

wherein the communication interface is a Fibre Channel interface having a serial transfer rate of at least 1 gigabit/second.

3. The protocol analyzer of

claim 1

wherein the host port is a PC parallel port.

4. The protocol analyzer of

claim 1

wherein the interface port provides a pair of channel connections to the communication interface and the trace buffer is divided into dual channels, one channel that stores traces from a first channel connection and another channel that stores traces from a second channel connection.

5. The protocol analyzer of

claim 1

wherein the hardware search engine searches the entire contents of the trace buffer for a specified data pattern in less than 10 seconds.

6. The protocol analyzer of

claim 1

wherein the portable chassis is less than 750 cubic inches and weighs less than 10 pounds.

7. The protocol analyzer of

claim 1

wherein hardware search engine searches the contents of the trace buffer at a speed of greater than 1 Mbyte every 20 milliseconds.

8. The protocol analyzer of

claim 1

wherein the trace buffer comprises at least two interleaved banks of memory formed of at least two megabytes of dynamic random access memory (DRAM) chips and wherein the traces are stored in each bank of the trace buffer on alternating clock cycles such that the DRAM chips are refreshed on the opposite alternating clock cycles.

9. The protocol analyzer of

claim 1

wherein the logic circuitry includes:

a dual port memory connected the interface port and the trace buffer to serve as a first-in, first out (fifo) buffer;

addressing circuitry connected to the dual port memory and the trace buffer having an write address counter, a read address counter and an address full counter; and

decision circuitry connected to the addressing circuitry and the dual port memory to analyze data in the fifo buffer and determine whether the data in the fifo buffer is a trace to be stored in the trace buffer.

10. The protocol analyzer of

claim 1

wherein the hardware search engine comprises:

a pattern memory loaded with the desired data pattern;

an address counter containing an address in the trace buffer to initiate; and

a comparator connected to the pattern memory and the trace buffer.

11. A system for analyzing a communication interface comprising:

a host processor that includes;

a user interface;

a computer processor; and

a main memory;

a protocol analyzer distinct from the host processor that includes;

a host port that provides a connection to the host processor;

an interface port that provides a connection to the communication interface;

a trace buffer memory;

logic circuitry that controls selective write operations of traces from the interface port to the trace buffer and selective read operations of traces from the trace buffer to the host port in response to parameters as directed by the host processor; and

a hardware search engine that locates specified data patterns as directed by the host processor within the trace buffer.

12. The system of

claim 11

wherein the communication interface is a Fibre Channel interface having a serial transfer rate of at least 1 gigabit/second.

13. The system of

claim 11

wherein the host processor is a laptop computer and the protocol analyzer is housed in a portable chassis separate from the laptop computer and the host port is a PC parallel port.

14. The system of

claim 11

wherein the host port provides a bus interface between the protocol analyzer and the host processor separate from an interface between the trace buffer and the hardware search engine of the protocol analyzer and separate from a bus interface between computer processor and the memory of the host processor.

15. The system of

claim 11

wherein the interface port provides a pair of channel connections to the communication interface and the trace buffer is divided into dual channels, one channel that stores traces from a first channel connection and another channel that stores traces from a second channel connection.

16. The system of

claim 11

wherein the hardware search engine searches the entire contents of the trace buffer for a specified data pattern in less than 10 seconds.

17. The system of

claim 11

wherein thehardware search engine searches the contents of the trace buffer at a speed of greater than 1 Mbyte every 20 milliseconds.

18. The system of

claim 11

wherein the trace buffer comprises at least two interleaved banks of memory formed of at least two megabytes of dynamic random access memory (DRAM) chips and wherein the traces are stored in each bank of the trace buffer on alternating clock cycles such that the DRAM chips are refreshed on the opposite alternating clock cycles.

19. The system of

claim 11

wherein the logic circuitry includes:

a dual port memory connected the interface port and the trace buffer to serve as a first-in, first out (fifo) buffer;

addressing circuitry connected to the dual port memory and the trace buffer having an write address counter, a read address counter and an address fill counter; and

decision circuitry connected to the addressing circuitry and the dual port memory to analyze data in the fifo buffer and determine whether the data in the fifo buffer is a trace to be stored in the trace buffer.

20. The system of

claim 11

wherein the hardware search engine comprises:

a pattern memory loaded with the desired data pattern;

an address counter containing an address in the trace buffer to initiate; and

a comparator connected to the pattern memory and the trace buffer.

21. A method of managing memory of a deep trace buffer of a protocol analyzer for a communication interface comprising:

(a) selectively writing traces from the communication interface into the trace buffer of the protocol analyzer,

(b) using a hardware search engine in the protocol analyzer to identify portions of the traces in the trace buffer matching a specified data pattern as determined by a host processor having a computer processor and a main memory separate from the trace buffer of the protocol analyzer; and

(c) in response to step (b), selectively reading at least a portion of the traces from the buffer to the host processor.