Semiconductor device having sidewall spacers manifesting a self-aligned contact hole

• US 20010017423A1
• Filed: 03/22/2001
• Published: 08/30/2001
• Est. Priority Date: 12/27/1996
• Status: Abandoned Application

• Current Assignee: LG Semicon Co Ltd (SK Hynix Inc.)
• Original Assignee: LG Semicon Co Ltd (SK Hynix Inc.)
• Inventors: Roh, Jae Sung, Yang, Woun S.
• Application Number:
  US09/813,834
• Publication Number:
  US 20010017423A1
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures

Abstract

A semiconductor device and a method for manufacturing the same that forms a self-aligned contact hole between two gate lines. A substrate is provided that has a first gate line formed thereon. An insulator is formed on the first gate line and substrate. Then a portion of the insulator and a portion of the first gate line is selectively removed to split the first gate line into a second gate line and a third gate line and to concurrently expose the substrate. Thus, producing a self-aligned contact hole between the second and third gate lines.

Claims

1. A semiconductor device having a self-aligned contact hole, the device comprising:

a substrate;

a first conductor structure and a second conductor structure formed on the substrate;

an insulator structure formed on the first and second conductor structure and on the substrate except over the substrate in a region between the first and second conductor structures; and

sidewall spacers, each sidewall spacer being formed to abut against both a side of the first or second conductor structures and a side of the insulator structure, the sidewall spacers manifesting the self-aligned contact hole in the region between the first and second conductor structures.

2. The semiconductor device of

claim 1

, wherein the first and second conductor structures are first and second gate structures, respectively.

3. The semiconductor device of

claim 1

, wherein the first and second conductor structures comprise:

a gate oxide layer formed on the substrate;

a conductive layer formed on the gate oxide layer; and

a gate cap insulating layer formed on the conductive layer.

4. The semiconductor device of

claim 1

, further comprising:

a contact plug formed in the self-aligned contact hole.

5. An unsymmetrical semiconductor device using a self-aligned contact hole, the device comprising:

a substrate having impurity regions formed therein;

a first conductor structure and a second conductor structure formed on the substrate except over the substrate in a region between the first and second conductor structures;

first sidewall spacers, each first sidewall spacer being formed to abut against both a side of the first or second conductor structures and a side of an insulator structure, the first sidewall spacers manifesting the self-aligned contact hole in the region between the first and second conductor structures; and

second sidewall spacers formed on sides of the first and second conductor structures opposite of the self-aligned contact hole.

6. The unsymmetrical semiconductor device of

claim 5

, wherein the ion concentration of a first impurity region is different than the ion concentration of a second impurity region.

7. The unsymmetrical semiconductor device of

claim 5

, further comprising:

a contact plug formed in the self-aligned contact hole, the contact plug being in contact with the first sidewall spacers and the first impurity region.

8. The unsymmetrical semiconductor device of

claim 7

, wherein the contact plug is also in contact with a bit line.

9. The unsymmetrical semiconductor device of

claim 7

, wherein the contact plug is not disposed directly above the first and second conductor structures.