Video line rate vertical scaler

• US 20010017631A1
• Filed: 03/23/2001
• Published: 08/30/2001
• Est. Priority Date: 10/09/1997
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Oakley, David
• Application Number:
  US09/815,771
• Publication Number:
  US 20010017631A1
• Time in Patent Office: Days
• US Class Current: 345/660
• CPC Class Codes: G06T 3/4023 based on decimating pixels or lines of pixels; based on inserting pixels or lines of pixels
• CPC Class Codes: H04N 5/14 Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 7/012 Conversion between an interlaced and a progressive signal for graphics images G09G2310/0229
• CPC Class Codes: H04N 7/0135 involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59
• CPC Class Codes: H04N 9/641 Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence

Abstract

For conversion of component (VGA) video to television, a hardware efficient process implements line rate vertical scaling within a single integrated circuit without the support of external memory. Scaling and filtering are combined into a single process which is a polyphase filter. The polyphase filter is a low pass filter with a fixed cut off frequency and a programmable delay. By changing the coefficients of the kernel of the polyphase filter, the scaled video signal is time shifted by fractions of the pixel clock. In one example, for every nine incoming horizontal video scan lines, eight lines are outputted thus accomplishing the vertical scaling. The vertical scaling may include a field buffer memory for accommodating a range of incoming video refresh rates, or in concert with special timing of incoming video, may omit the field buffer memory and instead use a one or two line FIFO memory.

Claims

1. A method for vertical scaling of an incoming video image, the video image being an array of pixels, the method comprising the steps of:

selecting at least four vertically adjacent pixels,

convolving the selected pixels adaptively by predetermined weights;

outputting a video image having n−

1 vertical lines for every n lines of the incoming video image.

2. The method of

claim 1

, where n=9.

3. The method of

claim 1

, wherein the step of convolving forms each pixel in the output video image selectively from three or four pixels of the original video image.

4. The method of

claim 1

, wherein the step of convolving uses exactly two sets of predetermined weights.

5. The method of

claim 1

, further comprising the step of storing an entire frame of the output video image, thereby to accommodate a plurality of refresh rates of the incoming video image.

6. The method of

claim 1

, further comprising the step of storing two or less lines of the output video image.

7. The method of

claim 1

, wherein the step of convolving includes multiplying each of the selected pixels by one of the predetermined weights, and adding the resulting products to arrive at a pixel in the output video image.

8. An apparatus for vertical scaling of an incoming video image, comprising:

an input port for receiving the incoming video image;

at least three series-connected line stores being coupled to the input port;

at least three multipliers, each multiplier having a first input port coupled to an output port of one of the line stores;

a modulo n counter having an input terminal coupled to receive a video line clock signal;

a decoder coupled to receive a count from the counter and storing at least two sets of coefficients, having one coefficient in each set for each multipliers, the decoder being coupled to a second input terminal of each multiplier;

an adder coupled to receive a product from the multipliers and to sum all the products; and

a memory to receive the summed products.

9. The apparatus of

claim 8

, wherein the memory is a field buffer memory.

10. The apparatus of

claim 8

, wherein the memory is a FIFO memory.

11. The apparatus of

claim 8

, wherein n=9.

12. The apparatus of

claim 8

, wherein the coefficients are such as to selectively convolve three or four pixels of the original video image.

13. An apparatus for vertical scaling of an incoming video image, comprising:

a port for receiving digitized incoming video data;

a terminal for receiving a horizontal line clock signal; and

a polyphase filter coupled to received the digitized video data and the clock signal and which convolves either three or four vertically adjacent pixels of the video data, using at least two different sets of coefficients, the set of coefficients for each output pixel being selected depending on a count of the horizontal line.