Method of forming a chip carrier by joining a laminate layer and stiffener

• US 20010018799A1
• Filed: 01/30/2001
• Published: 09/06/2001
• Est. Priority Date: 11/18/1998
• Status: Active Grant

• Current Assignee: David J. Russell, Heike Marcello, John M. Lauffer
• Original Assignee: David J. Russell, Heike Marcello, John M. Lauffer
• Inventors: Lauffer, John M., Russell, David J., Marcello, Heike
• Granted Patent: US 6,519,843 B2
• Time in Patent Office: Days
• US Class Current: 29/846
• CPC Class Codes: H01L 21/4803 Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks H01L21/4846 takes precedence; printed circuit boards H05K1/00
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/183 Components mounted in and supported by recessed areas of the printed circuit board
• CPC Class Codes: H05K 3/0023 by exposure and development of a photosensitive insulating layer
• CPC Class Codes: H05K 3/0061 onto a metallic substrate, e.g. a heat sink heat sinks for electric apparatus H05K7/20
• CPC Class Codes: H05K 3/386 by the use of an organic polymeric bonding layer, e.g. adhesive
• CPC Class Codes: Y10T 156/1798 with liquid adhesive or adhesive activator applying means
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49131 by utilizing optical sighting device
• CPC Class Codes: Y10T 29/49144 by metal fusion
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/53178 Chip component

Abstract

A cavity-type chip module. The module is formed with an adhesive joining layer of photoimageable material interposed between a metal stiffener and a laminate top layer with a central aperture defined in the top layer. The photoimageable material is exposed to actinic radiation, except for an area corresponding to the aperture in the top layer. The unexposed area of photoimageable material is developed away to form a window in the joining layer. The top layer, joining layer, and stiffener are laminated together with the window and aperture aligned, and with a portion of the stiffener spanning the aperture to define a cavity in the resulting substrate. The removal of the unexposed photoimageable material, and the selective exposure of the joining layer to actinic radiation, keep the cavity free of photoimageable material and inhibit bleeding of the photoimageable material into the cavity from its inner edge. As a result, a semiconductor component can be flush mounted in the cavity with optimal thermal conductivity to the metal stiffener.

Claims

1. A cavity-type chip module, comprising:

a circuitized laminate layer having opposite planar surfaces and an aperture, the aperture defined by an inner edge in the laminate layer and extending between the planar surfaces;

a planar metal stiffener disposed against one of the planar surfaces of the laminate layer to define respective opposing, mating surfaces, the stiffener having a mounting area spanning the aperture with a boundary defined by the inner edge of the aperture;

a joining layer interposed between the stiffener and the laminate layer and adhering the mating surfaces to each other, the joining layer being formed from a film of photoimageable material which has been developed to define a window substantially free of the material, the window having dimensions substantially similar to the dimensions of the aperture, the window and the aperture being substantially aligned with each other, whereby the photoimageable material is substantially absent from the mounting area; and

a chip secured to the mounting area and electrically coupled to the circuitized laminate layer, the chip having a planar chip surface disposed against the mounting area, the substantial absence of photoimageable material from the mounting area allowing the planar chip surface to be substantially flush against the mounting area.

2. The module of

claim 1

, wherein the chip has an outer perimeter and the mounting area is slightly larger than the outer perimeter of the chip, the module further comprising wire bonds extending from the inner edge of the aperture to corresponding locations on the chip.

3. The module of

claim 1

, wherein the joining layer further comprises at least one of the materials selected from the group consisting of coefficient of thermal expansion-varying material, electrically conductive material, thermally conductive material, and insulating material.

4. The module of

claim 1

, wherein the joining layer is applied to the mating surface of the stiffener.

5. The module of

claim 1

, wherein the joining layer is applied to the mating surface of the laminate layer.

6. The module of

claim 1

, wherein the laminate layer comprises a thin-light card.

7. The module of

claim 1

, wherein the joining layer comprises a first area of the photoimageable material exposed to sufficient radiation to inhibit bleeding of the material from the inner edge onto the mounting area, and a second area of the unexposed photoimageable material.

8. The module of

claim 7

, wherein the second area substantially corresponds in size and location to the window formed in the joining layer.

9. The module of

claim 8

, wherein the second area is slightly larger than the aperture defined in the laminate layer to facilitate placement of the aperture within the second area.

10. The module of

claim 1

, wherein the photoimageable material remains unexposed, a first area of the unexposed material is adhered between the stiffener and the laminate layer, and a second area of the unexposed material is subsequently developed to define the window in the joining area.

11. The module of

claim 2

, wherein the areas of the substrate adjacent to the inner edge of the aperture are adhered to the stiffener with substantially no separation of the inner edge from the stiffener.

12. The module of

claim 2

, wherein the joining layer is substantially free of air bubbles.

13. A printed circuit board comprising:

a circuitized first layer having opposite planar surfaces and an aperture defined in the first layer by an inner edge, the aperture extending between the planar surfaces;

a planar second layer disposed against one of the planar surfaces of the first layer to define respective opposing, mating surfaces, the second layer having a mounting area spanning the aperture with a boundary defined by the inner edge of the aperture; and

a joining layer interposed between the first and second layers and adhering the mating surfaces to each other, the joining layer being formed from a film of photoimageable material which has been selectively exposed to radiation and subsequently developed to define a window in the joining layer substantially free of the photoimageable material, the window having dimensions and a location substantially corresponding to the dimensions and location of the aperture, the window and the aperture being substantially aligned with each other, whereby the photoimageable material is substantially absent from the mounting area.

14. The printed circuit board of

claim 13

, wherein the first layer comprises a laminate layer and the printed circuit board comprises a laminate carrier for mounting chips thereon.

15. The printed circuit board of

claim 14

, wherein the mounting area is sized to receive a chip thereon, thereby defining a cavity-type laminate chip carrier.

16. The printed circuit board of

claim 14

, wherein the second layer comprises a metal stiffener.

17. The printed circuit board of

claim 13

, wherein the window is slightly larger than the aperture defined in the first layer to facilitate placement of the aperture within the area defined by the window.

18. In a method of forming a chip carrier in which a substantially planar, circuitized laminate layer and a corresponding stiffener are joined to each other, and in which the laminate layer has an aperture defined therein which exposes a corresponding mounting area on the stiffener, the aperture and the mounting area defining a cavity in the chip carrier, the improvement comprising the steps of:

applying a joining layer of adhesive material to at least one of the laminate layer and the stiffener;

exposing the adhesive material to radiation, excluding an area of the material having a size substantially similar to that of said aperture, the unexposed adhesive material being susceptible to removal from the joining layer;

laminating the laminate layer to the stiffener with the joining layer interposed therebetween; and

developing the cavity to remove the adhesive material therefrom to reveal the surface of the mounting area and render the mounting area substantially free of the adhesive material.

19. The method of

claim 18

, further comprising the steps of:

forming the joining layer from a film of photoimageable material; and

removing the unexposed photoimageable material when the cavity is developed.

20. The method of

claim 19

, further comprising the step of selectively exposing the photoimageable material surrounding the window to sufficient radiation to control the flow characteristics of the photoimageable material when subsequently laminated under heat and pressure.

21. The method of

claim 19

in which the aperture has an inner edge defining the boundary of the mounting area, and further comprising the step of inhibiting bleeding of the photoimageable material from the inner edge of the aperture into the mounting area by selective application of radiation, heat, and pressure to the photoimageable material to vary the flow characteristics of the photoimageable material.

22. The method of

claim 18

, further comprising the step of mounting an electronic component to the mounting area.

23. The method of

claim 22

, further comprising the step of forming the stiffener from copper, and wherein the mounting step comprises disposing a planar surface of the electronic component substantially flush against the mounting area to optimize thermal conductivity between the electronic component and the stiffener.

24. In a method of forming a chip carrier in which a substantially planar, circuitized laminate layer and a corresponding stiffener are joined to each other, and in which the laminate layer has an aperture defined therein which exposes a corresponding mounting area on the stiffener, the aperture and the mounting area defining a cavity in the chip carrier, the improvement comprising:

applying a joining layer of adhesive material to at least one of the laminate layer and the stiffener;

laminating the laminate layer to the stiffener with the joining layer interposed therebetween; and

developing the cavity to remove the adhesive material therefrom to reveal the surface of the mounting area and render the mounting area substantially free of the adhesive material; and

retaining in the chip carrier the adhesive material outside the cavity by means of contact by the laminate layer and the stiffener with the adhesive material.